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IDT77V106L25

CONTROL AND STATUS INTERFACE

Utility Bus

The Utility Bus is a byte-wide interface that provides access to the registers within the IDT77V106. These registers are used to select desired operating

characteristics and functions, and to communicate status to external systems.

The Utility Bus is implemented using a multiplexed address and data bus (AD[7:0]) where the register address is latched via the Address Latch Enable

(ALE) signal.

The Utility Bus interface is comprised of the following pins:

AD[7:0], ALE,

CS, RD, WR

Read Operation

Refer to the Utility Bus timing waveforms. A register read is performed as follows:

1.

Initialcondition:

—

— ALE not asserted (logic 0)

2.

Set up register address:

— place desired register address on AD[7:0]

— set ALE to logic 1;

— latch this address by setting ALE to logic 0.

3.

Read register data:

— Remove register address data from AD[7:0]

— assert

— assert

— wait minimum pulse width time (see AC specifications)

Write Operation

A register write is performed as described below:

1.

Initialcondition:

—

— ALE not asserted (logic 0)

2.

Set up register address:

— place desired register address on AD[7:0]

— set ALE to logic 1;

— latch this address by setting ALE to logic 0.

3.

Writedata:

— place data on AD[7:0]

— assert

— assert

Interrupt Operations

A variety of selectable interrupt and signalling conditions are provided. They are useful both during ‘normal’ operation, and as diagnostic aids. Refer to

the Status and Control Register List section.

Overall interrupt control is provided via bit 0 of the Master Control Register. When this bit is cleared (set to 0), interrupt signalling is prevented. The Interrupt

Mask Register allows individual masking of different interrupt sources. Additional interrupt signal control is provided by bit 5 of the Master Control Register.

When this bit is set (=1), receive cell errors will be flagged via interrupt signalling and all other interrupt conditions are masked. These errors include:

Normal interrupt operations are performed by setting bit 0 and clearing bit 5 in the Master Control Register.

INT (pin 34) will go to a low state when an

interrupt condition is detected. The external system should then interrogate the 77V106L25 to determine which one (or more) conditions caused this flag, and

resettheinterruptforfurtheroccurrences.ThisisaccomplishedbyreadingtheInterruptStatusRegister.Decodingthebitsinthisbytewilltellwhicherrorcondition

caused the interrupt. Reading this register also: