Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

IDT77V106L25 Datasheet(PDF) 9 Page - Integrated Device Technology

Part # IDT77V106L25
Description  3.3V ATM PHY for 25.6 and 51.2 Mbps
Download  27 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT77V106L25 Datasheet(HTML) 9 Page - Integrated Device Technology

Back Button IDT77V106L25 Datasheet HTML 5Page - Integrated Device Technology IDT77V106L25 Datasheet HTML 6Page - Integrated Device Technology IDT77V106L25 Datasheet HTML 7Page - Integrated Device Technology IDT77V106L25 Datasheet HTML 8Page - Integrated Device Technology IDT77V106L25 Datasheet HTML 9Page - Integrated Device Technology IDT77V106L25 Datasheet HTML 10Page - Integrated Device Technology IDT77V106L25 Datasheet HTML 11Page - Integrated Device Technology IDT77V106L25 Datasheet HTML 12Page - Integrated Device Technology IDT77V106L25 Datasheet HTML 13Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 27 page
background image
9
IDT77V106L25
In the transmit direction, the PHY first asserts TXCLAV (transmit cell available) to indicate that it has room in its transmit FIFO to accept at least one 53-byte
ATM cell. When the ATM layer device is ready to begin passing the cell, it asserts
TXEN (transmit enable) and TXSOC (start of cell), coincident with the first
byte of the cell on TXDATA.
TXEN can remain asserted for the duration of the cell transfer, or the ATM device may deassert TXEN at any time once the cell
transfer has begun; data is transferred only when
TXEN is asserted.
In the receive direction,
RXEN indicates when the ATM device is prepared to receive data. As with transmit, it may be asserted or deasserted at any time.
Note that this Utopia interface can be operated in either cell-mode or in byte-mode as determined by bit 1 in the Master Control Register. In cell-mode,
which is the default, the 77V106L25 does not assert TXCLAV until it has enough room in it’s transmit FIFO to accept a complete cell, and doesn’t assert RXCLAV
until it has a complete cell in the receive FIFO. It will not deassert TXCLAV or RXCLAV until at or near the end of the transfer of a cell.
In byte-mode, the phy can assert TXCLAV before it has room for a complete cell. It will modulate TXCLAV to prevent the FIFO from overflowing. Likewise,
it may assert RXCLAV before a complete cell has been received, and will modulate RXCLAV to prevent the FIFO from underflowing. There is generally little
advantage to the byte-mode, so most users will leave the 77V106L25 in the default cell-mode.
In both transmit and receive, TXSOC and RXSOC (start of cell) is asserted for one clock, coincident with the first byte of each cell. Odd parity is utilized
across each 8-bit data field, which means that for an all-zero pattern. the corresponding parity bit is one.
The following figures show examples of the Utopia Level 1 handshake.
TXCLK
TXSOC
TXCLAV
TXEN
TXDATA[7:0],
TXPARITY
X
H1
H2
P44
P45
P46
P47
P48
X
77v106 drw 16
.
TXCLK
TXSOC
TXCLAV
TXEN
TXDATA[7:0],
TXPARITY
P46
P47
P48
H1
H2
H3
H4
X
H5
77v106 drw 17
77v106 drw
Figure 4. Utopia Transmit Handshake - Single Cell
Figure 5. Utopia Transmit Handshake - Back to Back Cells and
TXEN Suspended Transmission


Similar Part No. - IDT77V106L25

ManufacturerPart #DatasheetDescription
logo
Integrated Device Techn...
IDT77V107 IDT-IDT77V107 Datasheet
325Kb / 24P
Single ATM PHY for 25.6 and 51.2 Mbps with Utopia Level 2
IDT77V107L25PF IDT-IDT77V107L25PF Datasheet
325Kb / 24P
Single ATM PHY for 25.6 and 51.2 Mbps with Utopia Level 2
IDT77V107L25PFI IDT-IDT77V107L25PFI Datasheet
325Kb / 24P
Single ATM PHY for 25.6 and 51.2 Mbps with Utopia Level 2
More results

Similar Description - IDT77V106L25

ManufacturerPart #DatasheetDescription
logo
Integrated Device Techn...
IDT77V1253 IDT-IDT77V1253 Datasheet
449Kb / 44P
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6 AND 51.2 MBPS ATM NETWORKS
IDT77V107 IDT-IDT77V107 Datasheet
325Kb / 24P
Single ATM PHY for 25.6 and 51.2 Mbps with Utopia Level 2
IDT77V1254L25 IDT-IDT77V1254L25 Datasheet
840Kb / 47P
Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks
IDT77V126L200 IDT-IDT77V126L200 Datasheet
229Kb / 30P
Single Port PHY (Physical Layer) for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications
IDT77V1264L200 IDT-IDT77V1264L200 Datasheet
390Kb / 49P
Quad Port PHY (Physical Layer) for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications
IDT77105 IDT-IDT77105 Datasheet
335Kb / 24P
PHY (TC-PMD) for 25.6 Mbps ATM Networks
logo
Bel Fuse Inc.
S558-5999-85 BEL-S558-5999-85 Datasheet
245Kb / 2P
ATM 25.6 MBPS INTERFACEMODULE
S553-1084-04 BEL-S553-1084-04 Datasheet
259Kb / 2P
ATM 25.6 MBPS INTERFACE MODULE
S556-2006-32 BEL-S556-2006-32 Datasheet
224Kb / 2P
ATM 25.6 MBPS FILTER MODULE
logo
Rhombus Industries Inc.
T-11229 RHOMBUS-IND-T-11229 Datasheet
29Kb / 1P
ATM 25.6 MBPS INTERFACE TRANSFORMER
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com