4

IDT77V106L25

Miscellaneous Signals

Signal Name

Pin Number

I/O

Signal Description

INT

34

Out

Interrupt

INT is an open-drain output, driven low to indicate an interrupt. Once low, INT remains low until

the interrupt status in the appropriate interrupt Status Register is read. Interrupt sources are programmable

via the interrupt Mast Registers.

OSC

52

In

TTL line rate clock source, driven by a 100 ppm oscillator. 32MHz for 25.63 Mbps; 65 MHz for 51.2 Mbps.

RST

35

In

Reset. Active low asynchronous input resets all control logic, counters and FIFOs. A reset must be performed

after power up prior to normal operation of the part.

RXLED

33

Out

Receive LED driver. Driven low for 223 cycles of OSC, beginning with RXSOC when a good (non-null and

non-errored) cell is received. Drives 8 mA both high and low.

RXREF

1

Out

Receive Reference. Active low.

RXREF pulses low for a programmable number of clock cycles when an

X_8 command byte is received.

SE

49

In

Reserved signal. This input must be connected to logic low.

SM

64

In

Reserved signal. This input must be connected to logic low.

TXLED

3

Out

Transmit LED driver. Goes low for 223 cycles of OSC, beginning with TXSOC when a cell is received for

transmission. 8 mA drive current both high and low.

TXREF

2

In

Transmit Reference. At the falling edge of

TXREF, an X_8 command byte is inserted into the transmit data

stream. Typical application is WAN timing.

TABLE 1 — SIGNAL DESCRIPTION (PART 2 OF 2)

Power Supply Signals

Signal Name

Pin Number

I/O

Signal Description

AGND

50, 53, 55

—

Analog ground. AGND is ground the analog portion of the ship, which sources a more constant current than

the digital portion.

AVDO

51, 54, 56

—

Analog power supply. AVDO supplies power to the analog portion of the chip, which draws a more constant

59

current than the digital portion. 3.3

±0.34V

GND

22, 44, 60

—

Digital Ground.

VDD

15, 28,63

—

Digital power supply. 3.3

± 0.3V