3

IDT77V106L25

Line Side Signals

Signal Name

Pin Number

I/O

Signal Description

RXD+, RXD-

58, 57

In

Positive and negative receive differential input pair.

TXD+, TXD-

62, 61

Out

Positive and negative transmit differential output pair.

Utility Bus Signals

Signal Name

Pin Number

I/O

Signal Description

AD[7:0]

48, 47, 46,

In/

Utility bus address/data bus. The address input is sampled on the falling edge of ALE. Data is output on this

45, 43, 42,

Out

bus when a read is performed. Input data is sampled at the completion of a write operation.

41, 40.

ALE

39

In

Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling

edge of ALE. ALE must be low when the AD bus is being used for data.

CS

38

In

Utility bus asynchronous chip select.

CSmustbeassertedtoreadorwriteaninternalregister. Itmayremain

asserted at all times if desired.

RD

37

In

Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by

deasserting

WR and asserting RD and CS.

WR

36

In

Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by

deasserting

RD, placing data on the AD bus, and asserting WR and CS. Data is sampled when WR or CS

is deasserted.

Utopia Bus Signals

Signal Name

Pin Number

I/O

Signal Description

RXCLAV

20

Out

Utopia Receive Cell Available. "1" indicates that the receive FIFO contains a complete cell. "0" indicates that

it does not.

RXCLK

18

In

Utopia Receive Clock. This is a free running clock input.

RXDATA[7:0]

24, 25, 26,

Out

Utopia Receive Data. When one of the four ports is selected, the 77V106L25 transfers received cells to an

27, 29, 30

ATM device across the bus. Also see RXPARITY.

31, 32.

RXEN

19

In

Utopia Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA

bus.

RXPARITY

23

Out

Utopia Receive Data Parity. Odd parity over RXDATA[7:0].

RXSOC

21

Out

Utopia Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA.

TXCLAV

16

Out

UtopiaTransmitCellAvailable."1"indicatesthatthetransmitFIFOhasroomavailableforatleastonecomplete

cell. "0" indicates that it does not.

TXCLK

17

In

Utopia Transmit Clock. This is a free running clock input.

TXDATA[7:0]

11, 10, 9, 8

In

Utopia Transmit Data. An ATM device transfer cell across this bus to the 77V106L25 for transmission. Also

7, 6, 5, 4

see TXPARITY.

TXEN

13

In

Utopia Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA bus.

TXPARITY

12

In

Utopia Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is checked and errors are indicated

in the Interrupt Status Registers, as enabled in the Master Control Register. No other action is taken in the

even of an error. Tie high or low if unused.

TXSOC

14

In

Utopia Transmit Start of Cell. Asserted coincident with the first word the first word of data for each cell on

TXDATA.

TABLE 1 — SIGNAL DESCRIPTION (PART 1 OF 2)