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IDT77V106L25 Datasheet(PDF) 25 Page - Integrated Device Technology |
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IDT77V106L25 Datasheet(HTML) 25 Page - Integrated Device Technology |
25 / 27 page ![]() 25 IDT77V106L25 Symbol Parameter Min. Typ Max Unit Tcyc OSC cycle period (25.6 Mbps) 30 31.25 33 ns (51.2 Mbps) 15 15.625 16.5 ns Tckh OSC high time 40 — 60 % Tckl OSC low time 40 — 60 % Tcc OSC Cycle to cycle period variation — — 1 % Ttrh TXREF High time 35 — — ns Ttrl TXREF Low time 35 — — ns Trspw Minimum RSTPulseWidth two OSC cycles — — — Trrpw RXREF Pulse Width (For default setting in register 0x03 0.9 1 1.1 Receive and 25.6 Mbps. Can be programmed for multiples (31.25ns) DataBit of this amount). Period OSC, TXREF and Reset Timing Note: The minimum RESET Pulse Width is either two RxCLK cycles, two TxCLK cycles, or two OSC cycles, whichever is greater (and applicable). 3505 drw 45 OSC RST Trspw TXREF Ttrl Ttrh Tcyc Tckh Tckl . RXREF Trrpw Figure 21. OSC, TXREF and Reset Timing Input Pulse Levels Gnd to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 22 AC Test Conditions Figure 22 1.2K Ω 30pF* 900 Ω 3.3V D.U.T. Figure 22. Output Load *Includes jig and scope capacitances. |
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