20

IDT77V106L25

LED Driver and HEC Status/Control Register

Address: 0x03

Bit

Type

Initial State

Function

7R

0

Reserved

6

R/W

0 = enable

Disable Receive HEC Checking (HEC Enable)

Checking

When not set, the HEC is calculated on first 4 bytes of received cell, and compared against the 5th byte. When set

(= 1), the HEC byte is not checked.

5

R/W

0 = enable

Disable Transmit HEC Calculate & Replace

calculate & When set, the 5th header byte of cells queued for transmit is not replaced with the HEC calculated across

the first four replace bytes of that cell.

4, 3

R/W

00 = 1 cycle

RxREF Pulse Width Select

Bit #4

3

0

0

RxREF active for 1 cycle of the recovered clock

0

1

RxREF active for 2 cycle of the recovered clock

1

0

RxREF active for 4 cycle of the recovered clock

1

1

RxREF active for 8 cycle of the recovered clock

2

R

1 = empty

Transmit FIFO Status 1 = TxFIFO empty

0 = TxFIFO not empty

1R

1

TxLED Status 0 = Cell Transmitted 1 = Cell Not Transmitted

0R

1

RxLED Status 0 = Cell Received

1 = Cell Not Received

Low Byte Counter Register [7:0]

Address: 0x04

Bit

Type

Initial State

Function

[7:0]

R

0x00

Provides low-byte of counter value selected via the Counter Select Register.

High Byte Counter Register [15:8]

Address: 0x05

Bit

Type

Initial State

Function

[7:0]

R

0x00

Provides high-byte of counter value selected via the Counter Select Register.

Counter Select Register

Address: 0x06

Bit

Type

Initial State

Function

7

—

0

Reserved

6

—

0

Reserved

5

—

0

Reserved

4

—

0

Reserved

3W

0

Symbol Error Counter

2W

0

Tx Cell Counter

1W

0

Rx Cell Counter Does not count HEC errored cells. even when bit 6 of the Master Control Register is Cleared.

0W

0

Receive Hec Error Counter

Note:

For proper operation, only one bit may be set in the Counter Selected Register at any time.