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IDT77V106L25 Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT77V106L25 Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 27 page  2 IDT77V106L25 77V106L25 OVERVIEW The 77V106L25 is a physical layer interface chip for 25.6Mbps ATM networkcommunicationsasdefinedbyATMForumdocumentaf-phy-040.000 and ITU-T I.432.5. The physical layer is divided into a Physical Media Dependent sub layer (PMD) and Transmission Convergence (TC) sub layer. ThePMDsublayerincludesthefunctionsforthetransmitter,receiverandclock recovery for operation across 100 meters of category 3 and 5 unshielded twisted pair (UTP) cable. This is referred to as the Line Side Interface. The TC sublayerdefinesthelinecoding,scrambling,dataframingandsynchronization. On the cell side, the 77V106L25 connects to an ATM layer device (such as a switch core or SAR) through an 8-bit Utopia Level 1 interface. The 77V106L25 is based on the 77105 and maintains significant register compatibility with it, but it also has additional register features. Access to these status and control registers is through the utility bus. This is an 8-bit muxed address and data bus, controlled by a conventional asynchronous read/write handshake. Additional pins permit insertion and extraction of an 8kHz timing marker, and provide LED indication of receive and transmit status. OPERATION AT 51.2 Mbps In addition to operation at the standard rate of 25.6 Mbps, the 77V106L25 isalsospecifiedtooperateat51.2Mbps.Exceptforthedoubledbitrate,allother aspects of operation are identical to the 25.6 Mbps mode. The rate is determined by the frequency of the clock applied to the OSC input pin. OSC is 32 MHz for the 25.6 Mbps line rate, and 64 MHz for the 51.2 Mbps line rate. See Figure 16 for recommended line magnetics. Magnetics for 51.2 Mbps operation have a higher bandwidth than magnetics optimized for 25.6 Mbps. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RXREF TXREF TXLED TXDATA0 TXDATA1 TXDATA2 TXDATA3 TXDATA4 TXDATA5 TXDATA6 TXDATA7 TXEN TXSOC VDD TXCLAV 17 18 19 21 22 23 24 25 26 27 28 29 30 32 20 31 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 AD7 AD6 AD5 AD4 GND AD3 AD2 AD1 AD0 ALE CS RD WR RST INT RXLED 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 77v106 drw 02 TXPARITY 77v106 drw 02 Pin 1 Index IDT77V106 Figure 1. Pin Assignments |
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