18

IDT77V106L25

Status and Control Register List

Master Control Register

Address: 0x00

Interrupt Status Register

Address: 0x01

70

Reserved

6

R

0 = Bad Signal

Good Signal Bit. See definitions earlier in this data sheet

1 - Good Signal

1 - Bad Signal

5

sticky

0

HEC error cell received. Set when a HEC errors detected on received cell.

4

sticky

0

"Short Cel" Received

Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected when receiving

Start-of-Cell command bytes with fewer than 53 bytes between them"

3

sticky

0

Transmit Parity Error

If Bit 4 of the Master Control Register (Transmit Data Parity Check) is set, this interrupt flags a transmit data parity

error condition. Odd parity is used.

2

sticky

0

Receive Signal Condition Change. This interrupt is set when the received "signal" changes either from "bad to good"

from "good to bad".

1

sticky

0

Received Symbol Error. Set when an undefined 5-bit symbol is received.

0

sticky

0

Receive FIFO Overflow. Interrupt which indicates when the receive FIFO has filled and cannot accept additional data.

Bit

Type

Initial State

Function

Bit

Type

Initial State

Function

7

R/W

0 = OSC

Clock Multiplier. Controls whether or not the OSC reference clock inputs is multiplied by two to generate the line

clock. Multiplied by one

Cleared (0) = OSC is multiplied by 1 to generate line clock

Set (1) = OSC is multiplied by 2 to generate line clock

6

R/W

1 = discard

Discard Receive Error Cells

errored cells On receipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive HEC error (if

enabled), this cell will be discarded and will not enter the receive FIFO.

5

R/W

0 = all interrupts Enable Cell Error Interrupts Only

If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only "Received Cell Error" (as defined in

bit 6) to trigger interrupt line".

4

R/W

0 = disabled

Transmit Data Parity Cells

Directs TC to check parity of TxDATA against parity bit located in TXPARITY.

3

R/W

1 = discard

Discard Received Idle Cells

idle cells

Directs TC to discard received idle (VPI/VCI = 0 and GFC = 0) cells from PMD without signaling external systems.

2

R/W

0 = not halted

Halt Tx

Halts transmission of data from TC to PMD and forces the TxD output to the "0" state.

1

R/W

0 = cell mode

UTOPIA Mode Select

0 = cell mode, 1 = byte mode.

0

R/W

1 = enable

Enable Interrupt Pin (Interrupt Mask Bit)

interrupts

Enables the

INT output pin. If cleared, pin is always high and interrupt is masked. If set, an interrupt will be signaled

by setting the interrupt pin to "0". It doesn't affect the Interrupt Status Registers".

Nomenclature

"Reserved" register bits, if written, should always be written "0"

R/W = register may be read and written via the utility bus

R-only or W-only = register is read-only or write only

sticky = register bit is cleared after the register containing it is read; all sticky bits are read-only

"0" = "cleared" or "not set"

"1" = "set"