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TLV2372IDG4 Datasheet(PDF) 28 Page - Texas Instruments |
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TLV2372IDG4 Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 58 page  - 55 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( C) ° 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 SOT-23 Package Low-K Test PCB = 324 q JA ° C/W SOIC Package Low-K Test PCB = 176 q JA ° C/W PDIP Package Low-K Test PCB = 104 q JA ° C/W MSOP Package Low-K Test PCB = 260 q JA ° C/W T = 150 C J ° P = D T T MAX A JA - q N/C –IN +IN V– N/C V+ OUTPUT N/C Use low-ESR, ceramic bypass capacitor GND VS+ Run the input traces as far away from the supply lines as possible Place components close to device and to eachother to reduce parasitic errors GND VIN RF GND RG Use low-ESR, ceramic bypass capacitor VS– VOUT Copyright © 2016, Texas Instruments Incorporated 28 TLV2370, TLV2371, TLV2372 TLV2373, TLV2374, TLV2375 SLOS270F – MARCH 2001 – REVISED AUGUST 2016 www.ti.com Product Folder Links: TLV2370 TLV2371 TLV2372 TLV2373 TLV2374 TLV2375 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Layout Example (continued) Figure 41. Operational Amplifier Board Layout for Noninverting Configuration 11.3 Power Dissipation Considerations For a given θJA, the maximum power dissipation is shown in Figure 42 and is calculated by Equation 4: where • PD = Maximum power dissipation of TLV237x IC (watts) • TMAX = Absolute maximum junction temperature (150°C) • TA = Free-ambient air temperature (°C) • θJA = θJC (Thermal coefficient from junction to case) + θCA (Thermal coefficient from case to ambient air (°C/W)) (4) Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 42. Maximum Power Dissipation vs Free-Air Temperature |
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