Host

MISO

MOSI

SCK

SS

LMH0395

MOSI

MISO

LMH0395

MOSI

MISO

LMH0395

MOSI

MISO

LMH0395

MOSI

MISO

Device 1

Device 2

Device 3

Device N

LMH0395

www.ti.com

SNLS323M – AUGUST 2010 – REVISED JULY 2015

Programming (continued)

In order to facilitate daisy-chaining, the prior SPI command, address, and data are shifted out on the MISO

output as the current command, address, and data are shifted in on the MOSI input. For SPI writes, the MISO

output is typically ignored as “Don't Care” data. For SPI reads, the MISO output provides the requested read data

(after 16 periods of SCK). The MISO output is active when SS low, and tri-stated when SS is high.

7.5.1.2 SPI Write

The SPI write is shown in Figure 2. The SPI write is 16 bits long. The 16-bit MOSI payload consists of a “0” (write

command), seven address bits, and eight data bits. The SS signal is driven low, and the 16 bits are sent to the

LMH0395's MOSI input. After the SPI write, SS must return high. The prior SPI command, address, and data

shifted out on the MISO output during the SPI write is shown as “Don't Care” on the MISO output in Figure 2.

7.5.1.3 SPI Read

The SPI read is shown in Figure 3. The SPI read is 32 bits long, consisting of a 16-bit read transaction followed

by a 16-bit dummy read transaction to shift out the read data on the MISO output. The first 16-bit MOSI payload

consists of a “1” (read command), seven address bits, and eight “1”s which are ignored. The second 16-bit MOSI

payload consists of 16 “1”s which are ignored but necessary in order to shift out the requested read data on the

MISO output. The SS signal is driven low, and the first 16 bits are sent to the LMH0395's MOSI input. The prior

SPI command, address, and data are shifted out on the MISO output during the first 16-bit transaction, and are

typically ignored (this is shown as “Don't Care” on the MISO output in Figure 3. SS must return high and then is

driven low again before the second 16 bits (all “1”s) are sent to the LMH0395's MOSI input. Once again, the prior

SPI command, address, and data are shifted out on the MISO output, but this data now includes the requested

read data. The read data is available on the MISO output during the second 8 bits of the 16-bit dummy read

transaction, as shown by D7-D0 in Figure 3.

7.5.1.4 SPI Daisy-Chain Operation

The LMH0395 SPI controller supports daisy-chaining the serial data between an unlimited number of LMH0395

devices. Each LMH0395 device is directly connected to the SCK and SS pins on the host. However, only the first

LMH0395 device in the chain is connected to the host’s MOSI pin, and only the last device in the chain is

connected to the host’s MISO pin. The MISO pin of each intermediate LMH0395 device in the chain is connected

to the MOSI pin of the next LMH0395 device, creating a serial shift register. This daisy-chain architecture is

shown in Figure 9.

Figure 9. SPI Daisy Chain System Architecture

In a daisy-chain configuration of N LMH0395 devices, the host conceptually sees a shift register of length 16xN.

Therefore the length of SPI transactions (as previously described) is 16xN bits, and SS must be asserted for

16xN clock cycles for each SPI transaction.

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