CD74HC4040M datasheet(7/15 Pages) TI

Part #	CD74HC4040M

Description	High-Speed CMOS Logic 12-Stage Binary Counter

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Manufacturer	TI [Texas Instruments]

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7

Qn to Qn + 1

tPLH, tPHL CL = 50pF

4.5

-

15

-

19

-

22

ns

CL =15pF

5

-

4

-

ns

MR to Qn

tPLH, tPHL CL = 50pF

4.5

-

40

-

50

-

60

ns

CL =15pF

5

-

17

-

ns

Output Transition

tTLH,tTHL CL = 50pF

4.5

-

15

-

19

-

22

ns

Input Capacitance

CIN

CL =15pF

-

10

-

10

-

10

pF

Power Dissipation

Capacitance (Notes 3, 4)

CPD

CL =15pF

5

-

45

-

pF

NOTES:

3. CPD is used to determine the dynamic power consumption, per package.

4. PD =VCC

2 f

i + ∑ (CLVCC

2 fi/M) where: M = 21,22,23, ...212,f

i = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

VCC (V)

25oC

-40oC TO

85oC

-55oC TO

125oC

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

Test Circuits and Waveforms

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

FIGURE 3. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CLOCK

90%

50%

10%

GND

VCC

trCL

tfCL

50%

tWL

tWH

10%

tWL + tWH =

fCL

I

CLOCK

2.7V

1.3V

0.3V

GND

3V

trCL = 6ns

tfCL = 6ns

1.3V

tWL

tWH

0.3V

tWL + tWH =

fCL

I

tPHL

tPLH

tTHL

tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns

tf = 6ns

90%

tPHL

tPLH

tTHL

tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

3V

tr = 6ns

tf = 6ns

90%

CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040

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CD74HC4040M Datasheet(PDF) 7 Page - Texas Instruments

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