LM3242

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SNOSB48E – OCTOBER 2011 – REVISED AUGUST 2015

Layout Guidelines (continued)

10.1.3.1 Component Placement

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PVIN

chain PVIN connection to LM3242 circuit and then to PA device PVIN connection.

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TOP LAYER

1. Place a via in LM3242 SGND(A2), BPEN(C1) pads to drop and connect directly to System GND Layer 4.

2. Place two vias at LM3242 SW solder bump to drop VSW trace to Layer 3.

3. Connect C2 and C3 capacitor GND pads to PGND bump on LM3242 using a star connection. Place vias

in C2 and C3 GND pads that connect directly to System GND Layer 4.

4. Add 01005/0201 capacitor footprints (C1, C4) to input/output of LM3242 for improved high frequency

filtering. C1 and C4 GND pads connect directly to System GND Layer 4.

5. Place three vias at L1 inductor pad to bring up VSW trace from Layer 3 to top Layer.

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LAYER 2

1. Make FB trace at least 10 mils (0.254 mm) wide.

2. Isolate FB trace away from noisy nodes and connect directly to C3 output capacitor. Place a via in

LM3242 SGND(A2), BPEN(C1) pads to drop and connect directly to System GND Layer 4.

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LAYER 3

1. Make VSW trace at least 15 mils (0.381 mm) wide.

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LAYER 4 (System GND

1. Connect C2 and C3 PGND vias to this layer.

2. Connect C1 and C4 GND vias to this layer.

3. Connect LM3242 SGND(A2), BPEN(C1), NC(B2) pad vias to this layer.

10.2 Layout Examples

Figure 33. Board Layer 1 – PVIN and PGND Routing

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Product Folder Links: LM3242