LM3242

SNOSB48E – OCTOBER 2011 – REVISED AUGUST 2015

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Layout Guidelines (continued)

10.1.2 Manufacturing Considerations

The LM3242 package employs a 9-pin (3 mm × 3 mm) array of 250 micron solder balls, with a 0.4-mm pad pitch.

A few simple design rules go a long way to ensuring a good layout.

•

Pad size must be 0.225 ± 0.02 mm. Solder mask opening must be 0.325 ± 0.02 mm.

•

As a thermal relief, connect to each pad with 7 mil wide, 7 mil long traces, and incrementally increase each

trace to its optimal width. Symmetry is important to ensure the solder bumps re-flow evenly (refer to TI

Application Note AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009).

10.1.3 LM3242 Evaluation Board

The following figures are drawn from a 4-layer board design, with notes added to highlight specific details of the

DC-DC switching converter section.

Figure 31. Simplified LM3242 RF Evaluation Board Schematic

1. Bulk Input Capacitor C2 must be placed closer to LM3242 than C1.

2. Add a 1nF (C1) on input of LM3242 for high frequency filtering.

3. Bulk Output Capacitor C3 must be placed closer to LM3242 than C4.

4. Add a 1nF (C4) on output of LM3242 for high frequency filtering.

5. Connect both GND terminals of C1 and C4 directly to System GND layer of phone board.

6. Connect bumps SGND (A2), NC (B2), BPEN (C1) directly to System GND.

7. Use 0402 caps for both C2 and C3 due to better high frequency filtering characteristics over 0603 capacitors.

8. TI has seen some improvement in high frequency filtering for small bypass caps (C1 and C4) when they are

connected to System GND instead of same ground as PGND. These capacitors must be 01005 case size for

minimum footprint and best high frequency characteristics.

Figure 32. LM3242 Recommended Parts Placement (Top View)

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