REV. 0

–10–

ADV7125

Therefore, if we have a graphics system with a 1024

× 1024

resolution, a noninterlaced 60 Hz refresh rate, and a retrace

factor of 0.8, then:

Dot Rate

=×

×

1024

1024

60 0 8

/.

= 78 6

.

MHz

The required CLOCK frequency is thus 78.6 MHz.

All video data and control inputs are latched into the ADV7125

on the rising edge of CLOCK, as previously described in the

Digital Inputs section. It is recommended that the CLOCK

input to the ADV7125 be driven by a TTL buffer (e.g., 74F244).

Video Synchronization and Control

The ADV7125 has a single composite sync (

SYNC) input con-

trol. Many graphics processors and CRT controllers have the

ability to generate horizontal sync (HSYNC), vertical sync

(VSYNC), and composite

SYNC.

In a graphics system that does not automatically generate a

composite

SYNC signal, the inclusion of some additional logic

circuitry enables the generation of a composite

SYNC signal.

The sync current is internally connected directly to the IOG

output, thus encoding video synchronization information onto

the green video channel. If it is not required to encode sync

information onto the ADV7125, the

SYNC input should be tied

to logic low.

Reference Input

The ADV7125 contains an on-board voltage reference. The

µF capaci-

tor. Alternatively, the part could, if required, be overdriven by

an external 1.23 V reference (AD1580).

determines the amplitude of the output video level according to

Equations 1 and 2 for the ADV7125:

IOG

mA

V

V

R

REF

SET

*

()

( )

11 444 8

,.

/

Ω

(1)

IOR IOB mA

V

V

R

REF

SET

,,

.

/

()

( )

7 989 6

Ω

(2)

*Applies to the ADV7125 only when SYNC is being used. If SYNC is not being

encoded onto the green channel, Equation 1 will be similar to Equation 2.

the analog output video levels. Use of a fixed 560

yields the analog output levels quoted in the specification page.

These values typically correspond to the RS-343A video wave-

form values as shown in Figure 3.

DACs

The ADV7125 contains three matched 8-bit DACs. The DACs

are designed using an advanced, high speed, segmented archi-

tecture. The bit currents corresponding to each digital input are

routed to either the analog output (bit = “1”) or GND (bit = “0”)

by a sophisticated decoding scheme. As all this circuitry is on

one monolithic device, matching between the three DACs is

optimized. As well as matching, the use of identical current sources

in a monolithic design guarantees monotonicity and low glitch.

The on-board operational amplifier stabilizes the full-scale

output current against temperature and power supply variations.

Analog Outputs

The ADV7125 has three analog outputs, corresponding to the

red, green, and blue video signals.

The red, green, and blue analog outputs of the ADV7125 are

high impedance current sources. Each one of these three RGB

current outputs is capable of directly driving a 37.5

Ω load,

such as a doubly terminated 75

Ω coaxial cable. Figure 4a

shows the required configuration for each of the three RGB

outputs connected into a doubly terminated 75

Ω load. This

arrangement develops RS-343A video output voltage levels

across a 75

Ω monitor.

A suggested method of driving RS-170 video levels into a 75

Ω

monitor is shown in Figure 4b. The output current levels of the

DACs remain unchanged, but the source termination resistance,

Ω to 150 Ω.

IOR, IOG, IOB

(CABLE)

(SOURCE

TERMINATION)

TERMINATION REPEATED THREE TIMES

FOR RED, GREEN, AND BLUE DACs

(MONITOR)

DACs



Figure 4a. Analog Output Termination for RS-343A

IOR, IOG, IOB

(CABLE)

(SOURCE

TERMINATION)

TERMINATION REPEATED THREE TIMES

FOR RED, GREEN, AND BLUE DACs

(MONITOR)

DACs



Figure 4b. Analog Output Termination for RS-170

More detailed information regarding load terminations for various

output configurations, including RS-343A and RS-170, is avail-

able in an application note entitled, Video Formats and Required

Load Terminations available from Analog Devices,

(www.analog.com/library/applicationNotes/video/AN205.pdf).

Figure 3 shows the video waveforms associated with the three RGB

outputs driving the doubly terminated 75

Ω load of Figure 4a. As

well as the gray scale levels (black level to white level), the diagram

also shows the contributions of

SYNC and BLANK for the

ADV7125. These control inputs add appropriately weighted cur-

rents to the analog outputs, producing the specific output level

requirements for video applications. Table I details how the

SYNC

and

BLANK inputs modify the output levels.

Grayscale Operation

The ADV7125 can be used for standalone, grayscale (mono-

chrome) or composite video applications (i.e., only one channel

used for video information). Any one of the three channels, red,

green, or blue, can be used to input the digital video data. The

two unused video data channels should be tied to logical zero.

The unused analog outputs should be terminated with the same

load as that for the used channel. In other words, if the red