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ON

ZVCHG FET = OFF

OFF

CHG FET = ON

OFF

CHG FET = ON

0 V

3.3 V

0 V

V = VPACK*(1/2)

3.5 V (typ.)

0 V

”L” (1 V)

”L” (1 V)

0 V

Fast Charge Current

0 V and Precharge Current

0 A

0 V Charge

Mode

Precharge

Mode

Fast Charge Mode

REG

ZVCHG

GHD

DSG

Battery

Voltage

Charge

Current

Common FET

bq29312A

SLUS629A – JANUARY 2005 – REVISED AUGUST 2005

APPLICATION INFORMATION (continued)

Figure 10. Signal Timing of Pins During 0-V Charging and Precharging (0-V Charge FET)

This mode does not require a dedicated precharge FET (ZVCHG-FET). The charge FET (CHG-FET) is ON at

circuit is shown in Figure 11. The charger is expected to provide the precharge function in this mode, where the

charger provides a precharge current level suitable to charge cells below a set level, typically below 3 V per cell.

When the lowest cell voltage rises above this level, then a fast charging current is applied.

When the charger is connected, the voltage at PMS rises. Once it is above 0.7 V, the CHG output is driven to

GND which turns ON the CHG-FET. The charging current flows through the CHG-FET and a back diode of

DSG-FET. The pack voltage is represented by the following equation.

V

under the bq29312A supply voltage, then the bq29312A regulator is inactive and the host controller is not

functional. Thus, any protection features of this chipset do not function during this period. This state continues

3.3-V (typ) supply to the host. When this level is reached, the CHG pin changes its state from GND to the level

controlled with CHG bit in bq29312A registers. In this state, the CHG output level is driven by a clamp circuit so

that its voltage level changes from 0 V to 1 V. Also, the host controller is active and can turn ON the DSG-FET.

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