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CDCLVP111-EP Datasheet(PDF) 7 Page - Texas Instruments |
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CDCLVP111-EP Datasheet(HTML) 7 Page - Texas Instruments |
7 / 15 page ![]() IL IH V V - CDCLVP111-EP www.ti.com SCAS933 – DECEMBER 2012 LVPECL DC ELECTRICAL CHARACTERISTICS Vsupply: VCC = 2.375 V to 3.8 V, VEE= 0 V over operating temperature range TJ = –55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IEE Supply internal current Absolute value of current –55°C, 25°C, 125°C 35 85 mA -55°C, 25°C 385 Output and internal ICC All outputs terminated 50 Ω to VCC – 2 V mA supply current 125°C 405 Includes pullup/pulldown resistors IIN Input current –55°C, 25°C, 125°C –150 150 μA VIH = VCC, VIL= VCC–2V VCC = 3 to 3.8 V, IBB= –0.2 mA –55°C, 25°C, 125°C VCC – 1.45 VCC – 1.3 VCC – 1.125 Internally generated VBB V VCC = 2.375 to 2.75 V, bias voltage –55°C, 25°C, 125°C VCC – 1.4 VCC – 1.25 VCC – 1.1 IBB = –0.2 mA High-level input voltage VIH –55°C, 25°C, 125°C VCC – 1.165 VCC – 0.88 V (CLK_SEL) Low-level input voltage VIL –55°C, 25°C, 125°C VCC – 1.81 VCC – 1.475 V (CLK_SEL) Input amplitude (CLKn, VID –55°C, 25°C, 125°C 0.5 1.3 V CLKn) Difference of inpu, see (1), Common-mode VCM DC offset relative to VEE –55°C, 25°C, 125°C 1 VCC – 0.3 V voltage (CLKn, CLKn) –55°C VCC – 1.26 VCC – 0.85 High-level output VOH IOH = –21 mA 25°C VCC – 1.2 VCC – 0.85 V voltage 125°C VCC – 1.15 VCC – 0.8 25°C VCC – 1.85 VCC – 1.425 Low-level output VOL IOL = –5 mA V voltage –55°C, 125°C VCC – 1.85 VCC – 1.25 Differential output Terminated with 50 Ω to VOD –55°C, 25°C, 125°C 400 mV voltage swing VCC - 2 V, See Figure 4 (1) VID minimum and maximum is required to maintain ac specifications, actual device function tolerates a minimum VID of 100 mV. AC ELECTRICAL CHARACTERISTICS Vsupply: VCC = 2.375 V to 3.8 V, VEE = 0 V or LVECL/LVPECL input VCC = 0 V, VEE = -2.375 V to -3.8 V over operating temperature range TJ = –55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Differential propagation delay CLKn, tpd See Note D in Figure 2 200 355 ps CLKn to all Q0, Q0… Q9, Q9 tsk(o) Output-to-output skew See Notes A and D in Figure 2 15 50 ps tsk(pp) Part-to-part skew See Notes B and D in Figure 2 70 ps Integration bandwidth of 20 kHz to 20 MHz, taj Additive phase jitter(1) 0.125 0.8 ps fout = 200 MHz at 25°C f(max) Maximum frequency(1) Functional up to 3.5 GHz, see Figure 4 3500 MHz tr/tf Output rise and fall time (20%, 80%) See Note D in Figure 2 240 ps (1) Specification is guaranteed by bench characterization and is not tested in production. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links :CDCLVP111-EP |
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