REV. A

–4–

AD7495–SPECIFICATIONS (continued)

Parameter

A Version

1

B Version

1

Unit

Test Conditions/Comments

CONVERSION RATE

Conversion Time

800

800

ns max

16 SCLK Cycles with SCLK at 20 MHz

Track/Hold Acquisition Time

300

300

ns max

Sine Wave Input

325

325

ns max

Full-Scale Step Input

Throughput Rate

1

1

MSPS max

See Serial Interface Section

POWER REQUIREMENTS

2.7/5.25

2.7/5.25

V min/max

2.7/5.25

2.7/5.25

V min/max

Normal Mode (Static)

1

1

mA typ

Normal Mode (Operational)

2.6

2.6

mA max

2

2

mA max

Partial Power-Down Mode

650

650

µA typ

Partial Power-Down Mode

230

230

µA max

(Static)

Full Power-Down Mode

1

1

µA max

(Static) SCLK On or Off

Power Dissipation

3

Normal Mode (Operational)

13

13

mW max

6

6

mW max

Partial Power-Down (Static)

1.15

1.15

mW max

690

690

µW max

Full Power-Down

5

5

µW max

33

µW max

NOTES

Specifications subject to change without notice.

otherwise noted.)

Parameter

AD7475/AD7495

Unit

Description

2

10

kHz min

20

MHz max

16

× t

SCLK

800

ns max

100

ns min

Minimum Quiet Time Required between Conversions

10

ns min

CS to SCLK Setup Time

3

22

ns max

Delay from

CS Until SDATA 3-State Disabled

3

40

ns max

Data Access Time after SCLK Falling Edge

ns min

SCLK Low Pulsewidth

ns min

SCLK High Pulsewidth

10

ns min

SCLK to Data Valid Hold Time

4

10

ns min

SCLK Falling Edge to SDATA High Impedance

45

ns max

SCLK Falling Edge to SDATA High Impedance

4

20

ns max

CS Rising Edge to SDATA High Impedance

20

µs max

Power-Up Time from Full Power-Down AD7475

650

µs max

Power-Up Time from Full Power-Down AD7495

NOTES

the true bus relinquish time of the part and are independent of the bus loading.

Specifications subject to change without notice.