REV. A

AD7475/AD7495

–15–

AD7475/AD7495*

SCLK

CS

DR

RFS

TFS

SDATA

ADSP-21xx*

SCLK

Figure 23. Interfacing to the ADSP-21xx

The Timer registers etc., are loaded with a value that will provide

an interrupt at the required sample interval. When an interrupt

is received, a value is transmitted with TFS/DT (ADC control

word). The TFS is used to control the RFS and hence the

reading of data. The frequency of the serial clock is set in the

SCLKDIV register. When the instruction to transmit with TFS

is given, (i.e., AX0 = TX0), the state of the SCLK is checked. The

DSP will wait until the SCLK has gone high, low, and high

before transmission will start. If the timer and SCLK values are

chosen such that the instruction to transmit occurs on or near

the rising edge of SCLK, the data may be transmitted or it may

wait until the next clock edge.

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3, an

SCLK of 2 MHz is obtained, and eight master clock periods will

elapse for every 1 SCLK period. If the timer registers are loaded

with the value 803, 100.5 SCLKs will occur between interrupts

and subsequently between transmit instructions. This situation

will result in nonequidistant sampling as the transmit instruc-

tion is occurring on a SCLK edge. If the number of SCLKs

between interrupts is a whole integer figure of N, equidistant

sampling will be implemented by the DSP.

AD7475/AD7495 to DSP56xxx

The connection diagram in Figure 24 shows how the AD7475/

AD7495 can be connected to the SSI (Synchronous Serial Inter-

face) of the DSP56xxx family of DSPs from Motorola. The SSI

is operated in Synchronous Mode (SYN bit in CRB = 1) with

internally generated 1-bit clock period frame sync for both Tx

and Rx (bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word

length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. To

implement the power-down modes on the AD7475/AD7495

then the word length can be changed to eight bits by setting bits

WL1 = 0 and WL0 = 0 in CRA. It should be noted that for

signal processing applications, it is imperative that the frame

synchronization signal from the DSP56xxx provide equidistant

same supply voltage as that of the DSP56xxx. This allows the

ADC to operate at a voltage higher than the serial interface, i.e.,

DSP56xxx, if necessary.

AD7475/AD7495*

SCLK

CS

SCLK

SC2

SDATA

DSP56xxx*

SRD

Figure 24. Interfacing to the DSP56xxx

AD7475/AD7495 to MC68HC16

The Serial Peripheral Interface (SPI) on the MC68HC16 is

configured for Master Mode (MSTR = 1), Clock Polarity Bit

(CPOL) = 1 and the Clock Phase Bit (CPHA) = 0. The SPI

is configured by writing to the SPI Control Register (SPCR), see

68HC16 user manual. The serial transfer will take place as a

16-bit operation when the SIZE bit in the SPCR register is

set to SIZE = 1. To implement the power-down modes with an

8-bit transfer set SIZE = 0. A connection diagram is shown in

supply voltage as that of the MC68HC16. This allows the ADC

to operate at a higher voltage than the serial interface, i.e.,

MC68HC16, if necessary.

AD7475/AD7495*

SCLK

CS

MISO/PMC0

SS/PMC3

SDATA

MC68HC16*

SCLK/PCM2

Figure 25. Interfacing to the MC68HC16