REV. A

AD7475/AD7495

–14–

The conversion is also initiated at this point and will require

16 SCLK cycles to complete. Once 13 SCLK falling edges have

elapsed, the track and hold will go back into track on the next

SCLK rising edge as shown in Figure 20 at Point B. On the

16th SCLK falling edge the SDATA line will go back into three-

state. If the rising edge of

CS occurs before 16 SCLKs have

elapsed, the conversion will be terminated and the SDATA line

will go back into three-state, as shown in Figure 21, otherwise

SDATA returns to three-state on the 16th SCLK falling edge as

shown in Figure 20.

Sixteen serial clock cycles are required to perform the conversion

process and to access data from the AD7475/AD7495.

CS going

low provides the first leading zero to be read in by the micro-

controller or DSP. The remaining data is then clocked out by

subsequent SCLK falling edges beginning with the 2nd leading

zero, thus the first falling clock edge on the serial clock has the

second leading zero provided. The final bit in the data transfer

is valid on the sixteenth falling edge, having being clocked out on

the previous (15th) falling edge.

In applications with a slower SCLK, it may be possible to read in

data on each SCLK rising edge, although the first leading zero will

still have to be read on the first SCLK falling edge after the

CS

falling edge. Therefore, the first rising edge of SCLK after the

CS

falling edge would provide the second leading zero and the 15th

rising SCLK edge would have DB0 provided. This method may

not work with most Micros/DSPs, but could possibly be used

with FPGAs and ASICs.

MICROPROCESSOR INTERFACING

The serial interface on the AD7475/AD7495 allows the parts to

be directly connected to a range of many different microprocessors.

This section explains how to interface the AD7475/AD7495 with

some of the more common microcontroller and DSP serial

interface protocols.

AD7475/AD7495 to TMS320C5x/C54x

The serial interface on the TMS320C5x/C54x uses a continuous

serial clock and frame synchronization signals to synchronize the

data transfer operations with peripheral devices like the AD7475/

AD7495. The

CS input allows easy interfacing between the

TMS320C5x/C54x and the AD7475/AD7495 without any glue

logic required. The serial port of the TMS320C5x/C54x is set

up to operate in burst mode with internal CLKX (Tx serial clock)

and FSX (Tx frame sync). The serial port control register (SPC)

must have the following setup: FO = 0, FSM = 1, MCM = 1 and

TXM = 1. The format bit, FO, may be set to 1 to set the word

length to 8 bits, in order to implement the power-down modes

on the AD7475/AD7495.

The connection diagram is shown in Figure 22. It should be noted

that for signal processing applications, it is imperative that

the frame synchronization signal from the TMS320C5x/C54x

AD7495 takes the same supply voltage as that of the TMS320C5x/

C54x. This allows the ADC to operate at a higher voltage than

the serial interface, i.e., TMS320C5x/C54x, if necessary.

AD7475/AD7495*

SCLK

CS

CLKX

DR

FBX

FSR

SDATA

TMS320C5x/C54x*

CLKR

Figure 22. Interfacing to the TMS320C5x/C54x

AD7475/AD7495 to ADSP-21xx

The ADSP-21xx family of DSPs are interfaced directly to the

of the AD7475/AD7495 takes the same supply voltage as that of

the ADSP-21xx. This allows the ADC to operate at a higher

voltage than the serial interface, i.e., ADSP-21xx, if necessary.

The SPORT control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

SLEN = 1111, 16-Bit Data Words

ISCLK = 1, Internal Serial Clock

TFSR = RFSR = 1, Frame Every Word

IRFS = 0,

ITFS = 1.

To implement the power-down modes SLEN should be set to

1001 to issue an 8-bit SCLK burst.

The connection diagram is shown in Figure 23. The ADSP-

21xx has the TFS and RFS of the SPORT tied together, with

TFS set as an output and RFS set as an input. The DSP oper-

ates in Alternate Framing Mode and the SPORT control register is

set up as described. The Frame synchronizations signal generated

on the TFS is tied to

CS and as with all signal processing appli-

cations equidistant sampling is necessary. However, in this

example, the timer interrupt is used to control the sampling rate

of the ADC and under certain conditions, equidistant sampling

may not be achieved.

SCLK

1

5

13

15

SDATA

FOUR LEADING ZEROS

THREE-STATE

2

34

16

THREE-STATE

DB11

DB10

DB2

14

0

0

0

0

B

CS

Figure 21. Serial Interface Timing Diagram—Conversion Termination