REV. A

AD7475/AD7495

–11–

before the 16th SCLK falling edge, the part will remain powered

up but the conversion will be terminated and SDATA will go

back into three-state. Sixteen serial clock cycles are required

to complete the conversion and access the conversion result.

CS

may idle high until the next conversion or may idle low until some-

time prior to the next conversion (effectively idling

CS low).

Once a data transfer is complete (SDATA has returned to

three-state), another conversion can be initiated after the quiet

Partial Power-Down Mode

This mode is intended for use in applications where slower

throughput rates are required; either the ADC is powered down

between each conversion, or a series of conversions may be

performed at a high throughput rate and then the ADC is powered

down for a relatively long duration between these bursts of several

conversions. When the AD7475 is in partial power-down, all ana-

log circuitry is powered down except for the bias current generator;

and, in the case of the AD7495, all analog circuitry is powered

down except for the on-chip reference and reference buffer.

To enter partial power-down, the conversion process must be

interrupted by bringing

CS high anywhere after the second falling

edge of SCLK and before the tenth falling edge of SCLK as shown

in Figure 14. Once

CS has been brought high in this window of

SCLKs, the part will enter partial power-down, and the con-

version that was initiated by the falling edge of

CS will be

terminated, and SDATA will go back into three-state. If

CS

is brought high before the second SCLK falling edge, the part

will remain in Normal Mode and will not power down. This will

avoid accidental power-down due to glitches on the

CS line.

In order to exit this mode of operation and power the AD7475/

AD7495 up again, a dummy conversion is performed. On the

falling edge of

CS the device will begin to power up, and will

continue to power up as long as

CS is held low until after the

falling edge of the tenth SCLK. The device will be fully powered

up once 16 SCLKs have elapsed, and valid data will result from

the next conversion as shown in Figure 15. If

CS is brought high

before the second falling edge of SCLK, the AD7475/AD7495

will go back into partial power-down again. This avoids accidental

power-up due to glitches on the

CS line; although the device

may begin to power up on the falling edge of

CS, it will power

down again on the rising edge of

CS. If in partial power-down

and

CS is brought high between the second and tenth falling

edges of SCLK, the device will enter full power-down mode.

Power-Up Time

The power-up time of the AD7475/AD7495 from partial power-

down is typically 1

µs, which means that with any frequency of

SCLK up to 20 MHz, one dummy cycle will always be suffi-

cient to allow the device to power up from partial power-down.

Once the dummy cycle is complete, the ADC will be fully pow-

ered up and the input signal will be acquired properly. The quiet

goes back into three-state after the dummy conversion, to the

next falling edge of

CS. When running at 1 MSPS throughput

rate, the AD7475/AD7495 will power up and acquire a signal

within

±0.5 LSB in one dummy cycle, i.e., 1 µs.

When powering up from the power-down mode with a dummy

cycle, as in Figure 15, the track-and-hold that was in hold mode

while the part was powered down, returns to track mode after the

first SCLK edge the part receives after the falling edge of

CS.

This is shown as Point A in Figure 15. Although at any SCLK

frequency one dummy cycle is sufficient to power the device up

SCLK

FOUR LEADING ZEROS + CONVERSION RESULT

SDATA

1

16

10

CS

Figure 13. Normal Mode Operation

SCLK

1

16

10

CS

2

Figure 14. Entering Partial Power-Down Mode

SCLK

CS

SDATA

INVALID DATA

VALID DATA

1

10

16

1

THE PART BEGINS

TO POWER UP

THE PART IS FULLY

POWERED UP

16

A

Figure 15. Exiting Partial Power-Down Mode