REV. A

AD7475/AD7495

–10–

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum source

impedance will depend on the amount of total harmonic distortion

(THD) that can be tolerated. The THD will increase as the source

impedance increases and performance will degrade. Figure 10

shows a graph of the total harmonic distortion versus source

impedance for various analog input frequencies.

SOURCE IMPEDANCE – Ohms

–90

1

100

–80

–70

–60

–50

10000

–40

10

1000

–30

–20

–10

Figure 10. THD vs. Source Impedance for Various Ana-

log Input Frequencies

Figure 11 shows a graph of total harmonic distortion versus analog

Input frequency for various supply voltages while sampling at

1 MSPS with an SCLK of 20 MHz.

INPUT FREQUENCY – kHz

10

100

–95

–93

–91

–87

1000

–85

–83

–81

–79

–77

–75

–89

Figure 11. THD vs. Analog Input Frequency for Various

Supply Voltages

Digital Inputs

The digital inputs applied to the AD7475/AD7495 are not limited

by the maximum ratings which limit the analog inputs. Instead,

the digital inputs applied can go to 7 V and are not restricted by

Another advantage of SCLK and

CS not being restricted by the

are avoided. If

CS or SCLK are applied before V

risk of latch-up as there would be on the analog inputs if a

allows the ADC to easily interface to both 3 V and 5 V processors.

The AD7475/AD7495 has better dynamic performance with a

more than 0.3 V. (See Absolute Maximum Ratings.)

Reference Section

An external reference source should be used to supply the 2.5 V

reference to the AD7475. Errors in the reference source will result

in gain errors in the AD7475 transfer function and will add the

specified full-scale errors on the part. A capacitor of at least 0.1

µF

should be placed on the REF IN pin. Suitable reference sources

for the AD7475 include the AD780, the AD680, and the AD1852.

The AD7495 contains an on-chip 2.5 V reference. As shown in

Figure 12, the voltage that appears at the REF OUT pin is inter-

nally buffered before being applied to the ADC, the output

impedance of this buffer is typically 10

Ω. The reference is capable

of sourcing up to 2 mA. The REF OUT pin should be decoupled

to AGND using a 100 nF or greater capacitor.

If the 2.5 V internal reference is to be used to drive another device

that is capable of glitching the reference at critical times, then the

reference will have to be buffered before driving the device. To

ensure optimum performance of the AD7495 it is recommended

that the Internal Reference not be over driven. If the use of an

external reference is required the AD7475 should be used.

V

REF OUT

25

40k

160k

Figure 12. AD7495 Reference Circuit

MODES OF OPERATION

The mode of operation of the AD7475/AD7495 is selected by

controlling the (logic) state of the

CS signal during a conversion.

There are three possible modes of operation, Normal Mode,

Partial Power-Down Mode, and Full Power-Down Mode. The

point at which

CS is pulled high after the conversion has been

initiated will determine which power-down mode, if any, the device

will enter. Similarly, if already in a power-down mode,

CS can

control whether the device will return to Normal operation or

remain in power-down. These modes of operation are designed to

provide flexible power management options. These options can be

chosen to optimize the power dissipation/throughput rate ratio for

differing application requirements.

Normal Mode

This mode is intended for fastest throughput rate performance as

the user does not have to worry about any power-up times with

the AD7475/AD7495 remaining fully powered all the time.

Figure 13 shows the general diagram of the operation of the

AD7475/AD7495 in this mode.

The conversion is initiated on the falling edge of

CS as described in

the Serial Interface section. To ensure the part remains fully pow-

ered up at all times,

CS must remain low until at least 10 SCLK

falling edges have elapsed after the falling edge of

CS. If CS is

brought high any time after the 10th SCLK falling edge, but