REV. A

AD7475/AD7495

–5–

SCLK

1

5

13

15

SDATA

FOUR LEADING ZEROS

THREE-STATE

2

34

16

THREE-STATE

DB11

DB10

DB2

DB0

14

0

0

0

0

B

DB1

CS

Figure 1. Serial Interface Timing Diagram

Timing Example 1

satisfying the minimum requirement of 100 ns.

Timing Example 2

of 100 ns. As in this example and with other slower clock values,

the signal may already be acquired before the conversion is

complete, but it is still necessary to leave 100 ns minimum

fully acquired at approximately Point C in Figure 2.

SCLK

1

5

13

15

2

34

16

14

B

CS

45ns

10ns

1/THROUGHPUT

C

Figure 2. Serial Interface Timing Example

200 A

200 A

50pF

TO OUTPUT

PIN

1.6V

Figure 3. Load Circuit for Digital Output Timing Specifications