CD54HC00_14 datasheet(5/15 Pages) TI1

Part #	CD54HC00

Description	High-Speed CMOS Logic Quad 2-Input NAND Gate

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5

Transition Times (Figure 1)

tTLH, tTHL CL = 50pF

2

-

75

-

95

18

110

ns

4.5

-

15

-

19

-

22

ns

6

-

13

-

16

-

19

ns

Input Capacitance

CI

-

10

-

10

-

10

pF

Power Dissipation Capacitance

(Notes 3, 4)

CPD

-

5

-

25

-

----

pF

HCT TYPES

Propagation Delay, Input to

Output (Figure 2)

tPLH, tPHL CL = 50pF

4.5

-

20

-

25

-

30

ns

Propagation Delay, Data Input to

Output Y

tPLH, tPHL CL = 15pF

5

-

8

-

----

pF

Transition Times (Figure 2)

tTLH, tTHL CL = 50pF

4.5

-

15

-

19

-

22

ns

Input Capacitance

CI

-

10

-

10

-

10

pF

Power Dissipation Capacitance

(Notes 3, 4)

CPD

-

5

-

25

-

----

pF

NOTES:

3. CPD is used to determine the dynamic power consumption, per gate.

4. PD = VCC

2 f

i (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

VCC

(V)

25oC

-40oC TO 85oC

-55oC TO 125oC

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

Test Circuits and Waveforms

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tPHL

tPLH

tTHL

tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns

tf = 6ns

90%

tPHL

tPLH

tTHL

tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

3V

tr = 6ns

tf = 6ns

90%

INPUT LEVEL

HC TYPES

HCT TYPES

VCC

3V

VS

50% VCC

1.3V

NOTE: Transition times and propagation delay times.

CD54HC00, CD74HC00, CD54HCT00, CD74HCT00

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