MICROWIRE

DEVICE

DAC124S085

CS

SK

SO

SCLK

DIN

SYNC

68HC11

DAC124S085

PC7

SCK

MOSI

SCLK

DIN

SYNC

18

DAC124S085

SNAS348G – MAY 2006 – REVISED APRIL 2016

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Programming (continued)

The 68HC11 must be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration

causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the

DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB

first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the

second byte of data to the DAC, after which PC7 must be raised to end the write sequence.

Figure 33. 68HC11 Interface

8.5.4 Microwire Interface

Figure 34 shows an interface between a Microwire compatible device and the DAC124S085. Data is clocked out

on the rising edges of the SK signal. As a result, the SK of the Microwire device must be inverted before driving

the SCLK of the DAC124S085.

Figure 34. Microwire Interface