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DAC124S085

SNAS348G – MAY 2006 – REVISED APRIL 2016

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Copyright © 2006–2016, Texas Instruments Incorporated

Feature Description (continued)

8.3.4 Power-On Reset

The power-on reset circuit controls the output voltages of the four DACs during power-up. Upon application of

power, the DAC registers are filled with zeros and the output voltages are 0 V. The outputs remain at 0 V until a

valid write sequence is made to the DAC.

8.4 Device Functional Modes

8.4.1 Power-Down Modes

The DAC124S085 has four power-down modes, two of which are identical. In power-down mode, the supply

current drops to 20 µA at 3 V and 30 µA at 5 V. The DAC124S085 is set in power-down mode by setting OP1

and OP0 to 11. Because this mode powers down all four DACs, the address bits, A1 and A0, are used to select

different output terminations for the DAC outputs. Setting A1 and A0 to 00 or 11 causes the outputs to be tri-

stated (a high impedance state). While setting A1 and A0 to 01 or 10 causes the outputs to be terminated by 2.5

k

Ω or 100 kΩ to ground respectively (see Table 1).

Table 1. Power-Down Modes

A1

A0

OP1

OP0

OPERATING MODE

0

0

1

1

High-Z outputs

0

1

1

1

2.5 k

Ω to GND

1

0

1

1

100 k

Ω to GND

1

1

1

1

High-Z outputs

The bias generator, output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the

power-down modes. However, the contents of the DAC registers are unaffected when in power down. Each DAC

register maintains its value prior to the ADC124S085 being powered down unless it is changed during the write

sequence which instructed it to recover from power down. Minimum power consumption is achieved in the

8.5 Programming

8.5.1 Serial Interface

The three-wire interface is compatible with SPI, QSPI, and MICROWIRE, as well as most DSPs and operates at

clock rates up to 40 MHz. See Timing Requirements for information on a write sequence.

into the 16-bit serial input register on the falling edges of SCLK. To avoid misclocking data into the shift register,

it is critical that SYNC not be brought low simultaneously with a falling edge of SCLK (see Figure 2). On the 16th

falling clock edge, the last data bit is clocked in and the programmed function (a change in the DAC channel

address, mode of operation, or register contents) is executed. At this point the SYNC line may be kept low or

brought high. Any data and clock pulses after the 16th falling clock edge are ignored. In either case, SYNC must

be brought high for the minimum specified time before the next write sequence is initiated with a falling edge of

SYNC.

sequences to minimize power consumption.

8.5.2 Input Shift Register

The input shift register, Figure 30, has sixteen bits. The first two bits are address bits. They determine whether

the register data is for DAC A, DAC B, DAC C, or DAC D. The address bits are followed by two bits that

determine the mode of operation (writing to a DAC register without updating the outputs of all four DACs, writing

to a DAC register and updating the outputs of all four DACs, writing to the register of all four DACs and updating

their outputs, or powering down all four outputs). The final twelve bits of the shift register are the data bits. The

data format is straight binary (MSB first, LSB last), with all 0s corresponding to an output of 0 V and all 1s

the DAC register on the sixteenth falling edge of SCLK (see Figure 2).