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DAC121S101QML Datasheet(PDF) 21 Page - Texas Instruments |
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DAC121S101QML Datasheet(HTML) 21 Page - Texas Instruments |
21 / 26 page ![]() DAC121S101QML www.ti.com SNAS410E – MAY 2008 – REVISED MARCH 2013 Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the board. The clock and data lines should have controlled impedances. Radiation Environments Careful consideration should be given to environmental conditions when using a product in a radiation environment. Total Ionizing Dose The products with the radiation hardness assurance (RHA) levels listed in the Ordering Information table listed on the front page are qualified for low dose rate environments only. DAC121S101WGRQV 5962R0722601VZA This product is tested and qualified per MIL-STD-883 Test Method 1019, Condition A and the “Extended room temperature anneal test” where a high dose irradiation followed by a room temperature anneal is used to simulate a dose rate of 0.027 rad(Si)/s and is qualified for environments with radiation levels of 0.027 rad(Si)/s or lower. DAC121S101WGRLV 5962R0722602VZA This product is tested and qualified per MIL-STD-883 Test Method 1019, Condition D at a dose rate of 0.01 rad(Si)/s and are qualified for environments with radiation levels of 0.01 rad(Si)/s or lower. Single Event Latch-Up and Functional Interrupt One time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was preformed according to EIA/JEDEC Standard, EIA/JEDEC57. The linear energy transfer threshold (LETth) shown in the Key Specifications section on the front page is the maximum LET tested. A test report is available upon request. Single Event Upset A report on single event upset (SEU) is available upon request. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: DAC121S101QML |
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