DB15 (MSB)

X

X

PD1 PD0 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DATA BITS

DB0 (LSB)

5 k:

100 k:

Power-Down Modes

0 0 Normal Operation

0 1

to GND

1 0

to GND

1 1 High Impedance

DAC121S101QML

SNAS410E – MAY 2008 – REVISED MARCH 2013

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sequences to minimize power consumption.

INPUT SHIFT REGISTER

The input shift register, Figure 34, has sixteen bits. The first two bits are "don't cares" and are followed by two

bits that determine the mode of operation (normal mode or one of three power-down modes). The contents of the

serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Timing

Diagram, Figure 4.

Figure 34. Input Register Contents

Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th

SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the shift register is reset and

the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation

or in the output voltage.

POWER-ON RESET

The power-on reset circuit controls the output voltage during power-up. Upon application of power the DAC

register is filled with zeros and the output voltage is 0 Volts and remains there until a valid write sequence is

made to the DAC.

POWER-DOWN MODES

The DAC121S101 has four modes of operation. These modes are set with two bits (DB13 and DB12) in the

control register.

Table 1. Modes of Operation

DB13

DB12

Operating Mode

0

0

Normal Operation

0

1

Power-Down with 5k

Ω to GND

1

0

Power-Down with 100k

Ω to GND

1

1

Power-Down with Hi-Z

When both DB13 and DB12 are 0, the device operates normally. For the other three possible combinations of

these bits the supply current drops to its power-down level and the output is pulled down with either a 5k

Ω or a

100k

Ω resistor, or is in a high impedance state, as described in Table 1.

The bias generator, output amplifier, the resistor string and other linear circuitry are all shut down in any of the

power-down modes. Minimum power consumption is achieved in the power-down mode with SCLK disabled and

16

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