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BQ24705 Datasheet(PDF) 8 Page - Texas Instruments |
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BQ24705 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 32 page bq24705 SLUS779B – DECEMBER 2007 – REVISED MARCH 2009............................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) 7 V ≤ VPVCC ≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PWM LOW SIDE DRIVER (LODRV) Low side driver turn-on resistance REGN = 6 V, tested at 100 mA 3 6 RDS(on) Ω Low side driver turn-off resistance REGN = 6 V, tested at 100 mA 0.6 1.2 PWM DRIVERS TIMING Driver Dead Time — Dead time when switching between LODRV and HIDRV. No 30 ns load at LODRV and HIDRV PWM OSCILLATOR FSW PWM switching frequency 480 600 720 kHz VRAMP_HEIGHT PWM ramp height As percentage of PVCC 6.6 %PVCC QUIESCENT CURRENT VBAT = 16.8 V, VACDET < 0.6 V, 7 10 VPVCC > 5 V, TJ = 85°C Total off-state battery current from SRP, IOFF_STATE µA SRN, BAT, VCC, BTST, PH, etc. VBAT = 16.8 V, VACDET < 0.6 V, 7 11 VPVCC > 5 V, TJ = 125°C IAC Adapter quiescent current VPVCC = 20 V, charge disabled 2.8 4 mA INTERNAL SOFT START (8 steps to regulation current) Soft start steps 8 step Soft start step time 1.7 ms CHARGER SECTION POWER-UP SEQUENCING Delay from when adapter is detected Charge-enable delay after power-up to when the charger is allowed to turn 518 700 908 ms on ISYNSET AMPLIFIER AND COMPARATOR (SYNCHRONOUS TO NON-SYNCHRONOUS TRANSITION) ISYN Accuracy V(SRP-SRN) = 5 mV –20% 20% ISYNSET pin voltage 1 V VISYNSET ISYNSET rising deglitch 20 µs ISYNSET falling deglitch 640 µs LOGIC IO PIN CHARACTERISTICS (CHGEN) VIN(LO) Input low threshold voltage 0.8 V VIN(HI) Input high threshold voltage 2.1 IBIAS Input bias current VCHGEN = 0 to VREGN 1 µA LOGIC INPUT PIN CHARACTERISTICS (CELLS) VIN(LO) Input low threshold voltage, 3 cells CELLS voltage falling edge 0.5 CELLS voltage rising for MIN, VIN(MID) Input mid threshold voltage, 2 cells 0.8 1.8 V CELLS voltage falling for MAX VIN(HI) Input high threshold voltage, 4 cells CELLS voltage rising 2.5 IBIAS_FLOAT Input bias float current for 2-cell selection V = 0 to VREGN –1 1 µA OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (DPMDET) VO(LO) Output low saturation voltage Sink Current = 5 mA 0.5 V Delay, rising/falling 10 ms 8 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24705 Not Recommended for New Designs |
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