bq24705

Table 1. TERMINAL FUNCTIONS – 24-PIN QFN

TERMINAL

DESCRIPTION

NAME

NO.

PVCC

1

IC power positive supply. Place a 0.1-

µF ceramic capacitor from PVCC to PGND pin close to the IC.

CHGEN

2

Charge enable active-low logic input. LO enables charge. HI disables charge.

Adapter current sense resistor, negative input. A 0.1-

µF ceramic capacitor is placed from ACN to ACP to provide

ACN

3

ACN 2 differential-mode filtering. An optional 0.1-

µF ceramic capacitor is placed from ACN pin to AGND for

common-mode filtering.

Adapter current sense resistor, positive input. A 0.1-

µF ceramic capacitor is placed from ACN to ACP to provide

ACP

4

differential-mode filtering. A 0.1-

µF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.

Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from

adapter input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V.

ACDET

5

overvoltage protection. It disables charge when ACDET > 3.1 V. ACOV does not latch and normal charge resumes

when ACDET<3.1V.

Adapter current set input. The voltage ratio of ACSET voltage versus VREF voltage programs the input current

ACSET

6

regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VREF

to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin.

Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout, connect to the

AGND

7

analog ground plane, and only connect to PGND through the PowerPad underneath the IC.

3.3-V regulated voltage output. Place a 1-

µF ceramic capacitor from VREF to AGND pin close to the IC. This voltage

VREF

8

could be used for ratiometric programming of voltage and current regulation. VREF is the source for the internal

circuit.

Charge voltage set input. The voltage ratio of VADJ voltage versus VREF voltage programs the battery voltage

VADJ

9

regulation set-point. Program by connecting a resistor divider from VREF to VADJ, to AGND; or, by connecting the

output of an external DAC to VADJ. VADJ connected to REGN programs the default of 4.2 V per cell.

Valid adapter active-low detect logic open-drain output. Pulled low when input voltage is above ACDET programmed

ACGOOD

10

threshold. Connect a 10-k

Ω pullup resistor from ACGOOD pin to pullup supply rail.

Synchronous mode current set input. Place a resistor from ISYNSET to AGND to program the charge undercurrent

ISYNSET

11

threshold to force non-synchronous converter operation at low output current, and to prevent negative inductor

current. Threshold should be set at greater than half of the maximum inductor ripple current (50% duty cycle).

Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a

IADAPT

12

100-pF or less ceramic decoupling capacitor from IADAPT to AGND.

Charge current set input. The voltage ratio of SRSET voltage versus VREF voltage programs the charge current

SRSET

13

regulation set-point. Program by connecting a resistor divider from VREF to SRSET to AGND; or by connecting the

output of an external DAC to SRSET pin.

Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the

BAT

14

BAT pin to accurately sense the battery pack voltage. Place a 0.1-

µF capacitor from BAT to AGND close to the IC to

filter high-frequency noise.

Charge current sense resistor, negative input. A 0.1-

µF ceramic capacitor is placed from SRN to SRP to provide

SRN

15

differential-mode filtering. An optional 0.1-

µF ceramic capacitor is placed from SRN pin to AGND for common-mode

filtering.

Charge current sense resistor, positive input. A 0.1-

µF ceramic capacitor is placed from SRN to SRP to provide

SRP

16

differential-mode filtering. A 0.1-

µF ceramic capacitor is placed from SRP pin to AGND for common-mode filtering.

CELLS

17

2, 3 or 4 cells selection logic input. Logic low programs 3 cell. Logic high programs 4 cell. Floating programs 2 cell.

Dynamic power management (DPM) input current loop active, open-drain output status. Logic low indicates input

DPMDET

18

current is being limited by reducing the charge current. Connect 10-k

Ω pullup resistor from DPMDET to VREF or a

different pullup-supply rail.

Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source

PGND

19

of low-side power MOSFET, to ground connection of in put and output capacitors of the charger. Only connect to

AGND through the PowerPad underneath the IC.

LODRV

20

PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.

PWM low side driver positive 6-V supply output. Connect a 1-

µF ceramic capacitor from REGN to PGND, close to the

REGN

21

IC. Use for high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST.

PWM high side driver negative supply. Connect to the phase switching node (junction of the low-side power

PH

22

MOSFET drain, high-side power MOSFET source, and output inductor). Connect the 0.1-

µF bootstrap capacitor from

from PH to BTST.

HIDRV

23

PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.

PWM high side driver positive supply. Connect a 0.1-

µF bootstrap ceramic capacitor from BTST to PH. Connect a

BTST

24

small bootstrap Schottky diode from REGN to BTST.

4

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