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DM74LS373N Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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DM74LS373N Datasheet(HTML) 2 Page - National Semiconductor (TI) |
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2 / 8 page  General Description (Continued) The eight latches of the DM5474LS373 are transparent D- type latches meaning that while the enable (G) is high the Q outputs will follow the data (D) inputs When the enable is taken low the output will be latched at the level of the data that was set up The eight flip-flops of the DM5474LS374 are edge-trig- gered D-type flip flops On the positive transition of the clock the Q outputs will be set to the logic states that were set up at the D inputs A buffered output control input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state In the high-impedance state the outputs neither load nor drive the bus lines signifi- cantly The output control does not affect the internal operation of the latches or flip-flops That is the old data can be retained or new data can be entered even while the outputs are off Function Tables DM5474LS373 Output Enable D Output Control G LH H H LH L L LL X Q0 HX X Z DM5474LS374 Output Clock D Output Control L u HH L u LL LL X Q0 HX X Z H e High Level (Steady State) L e Low Level (Steady State) X e Don’t Care u e Transition from low-to-high level Z e High Impedance State Q0 e The level of the output before steady-state input conditions were established Logic Diagrams DM5474LS373 Transparent Latches TLF6431 – 3 DM5474LS374 Positive-Edge-Triggered Flip-Flops TLF6431 – 4 2 |
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