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ADC12J1600 Datasheet(PDF) 77 Page - Texas Instruments

Part # ADC12J1600
Description  GSPS ADCs With Integrated DDC
Download  98 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12J1600 Datasheet(HTML) 77 Page - Texas Instruments

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ADC12J1600, ADC12J2700
www.ti.com
SLAS969C – JANUARY 2014 – REVISED JULY 2015
7.6.1.7.7
Overrange Threshold 0 Register (address = 0x206) [reset = 0xF2]
Figure 100. Overrange Threshold 0 Register (OVR_T0)
7
6
5
4
3
2
1
0
OVR_T0
R/W-1111 0010
Table 78. OVR_T0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
OVR_T0
R/W
1111 0010
Over-range threshold 0. This parameter defines the absolute
sample level that causes control bit 0 to be set. Control bit 0 is
attached to the DDC I output samples. The detection level in
dBFS (peak) is
20log10(OVR_T0 / 256)
Default: 0xF2 = 242
→ –0.5 dBFS
7.6.1.7.8
Overrange Threshold 1 Register (address = 0x207) [reset = 0xAB]
Figure 101. Overrange Threshold 1 Register (OVR_T1)
7
6
5
4
3
2
1
0
OVR_T1
R/W-1010 1011
Table 79. OVR_T1 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
OVR_T1
R/W
1010 1011
Overrange threshold 1. This parameter defines the absolute
sample level that causes control bit 1 to be set. Control bit 1 is
attached to the DDC Q output samples. The detection level in
dBFS (peak) is
20log10(OVR_T1 / 256)
Default: 0xAB = 171
→ –3.5 dBFS
7.6.1.7.9
Overrange Period Register (address = 0x208) [reset = 0x00]
Figure 102. Overrange Period Register (OVR_N)
7
6
5
4
3
2
1
0
RESERVED
OVR_N
R/W-0000 0
R/W-000
Table 80. OVR_N Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
0000 0
2-0
OVR_N(1)
R/W
000
This bit adjusts the monitoring period for the OVR[1:0] output
bits. The period is scaled by 2OVR_N. Incrementing this field
doubles the monitoring period.
(1)
Changing the OVR_N setting while JESD_EN=1 may cause the phase of the monitoring period to change.
Copyright © 2014–2015, Texas Instruments Incorporated
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Product Folder Links: ADC12J1600 ADC12J2700


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