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ADC12J1600 Datasheet(PDF) 13 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 13 Page - Texas Instruments |
13 / 98 page ![]() ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at TA = 25°C. (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –145 dBFS/Hz 50- Ω AC-coupled terminated input Noise spectral density, –146.8 dBm/Hz 12-bit DDC bypass mode, ADC12J1600, NSD average NSD across Nyquist ƒ(DEVCLK) = 1.6 GHz –143.9 dBFS/Hz bandwidth FIN = 600 MHz, –1 dBFS –145.7 dBm/Hz DECIMATE-BY-8 MODE, ADC12J2700, ƒ(DEVCLK) = 2.7 GHz 62.8 Signal-to-noise ratio, FIN = 600 MHz, –1 dBFS, decimate-by-8 integrated across DDC output mode SNR Calibration = BG 62.7 dBFS bandwidth Interleaving spurs included FIN = 2400 MHz, –1 dBFS, Decimate-by-8 mode 53.3 62.8 Signal-to-noise and distortion FIN = 600 MHz, –1 dBFS, decimate-by-8 ratio, integrated across DDC mode SINAD Calibration = BG 62.7 dBFS output bandwidth Interleaving spurs included FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 53.3 10.1 Effective number of bits, FIN = 600 MHz, –1 dBFS, decimate-by-8 integrated across DDC output mode ENOB Calibration = BG 10.1 Bits bandwidth Interleaving spurs included FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 8.6 75.9 Spurious-free dynamic range FIN = 600 MHz, –1 dBFS, decimate-by-8 SFDR dBFS Interleaving spurs included mode Calibration = BG 74.7 –73 Interleaving offset spur at ½ FIN = 600 MHz, –1 dBFS, decimate-by-8 ƒS/2 dBFS sampling rate (3) mode Calibration = BG –72 –70 Interleaving offset spur at ¼ FIN = 600 MHz, –1 dBFS, decimate-by-8 ƒS/4 dBFS sampling rate (3) mode Calibration = BG –70 Interleaving spur at ½ –80 FIN = 600 MHz, –1 dBFS, decimate-by-8 ƒS/2 – FIN sampling rate – input dBFS mode Calibration = BG –79 frequency (3) Interleaving spur at ¼ –73 FIN = 600 MHz, –1 dBFS, decimate-by-8 ƒS/4 + FIN sampling rate + input dBFS mode Calibration = BG –70 frequency (3) Interleaving spur at ¼ –77 FIN = 600 MHz, –1 dBFS, decimate-by-8 ƒS/4 – FIN sampling rate – input dBFS mode Calibration = BG –77 frequency (3) –70 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode THD Total harmonic distortion (3) calibration = BG –71 dBFS FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –65 –78 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode HD2 Second harmonic distortion (3) Calibration = BG –76 dBFS FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –67 –74 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode HD3 Third harmonic distortion (3) Calibration = BG –81 dBFS FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –73 DECIMATE-BY-8 MODE, ADC12J1600, ƒ(DEVCLK) = 1.6 GHz 63.5 Signal-to-noise ratio, FIN = 600 MHz, –1 dBFS, decimate-by-8 integrated across DDC output mode SNR Calibration = BG 63.4 dBFS bandwidth Interleaving spurs included FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 55.8 63.5 Signal-to-noise and distortion FIN = 600 MHz, –1 dBFS, decimate-by-8 ratio, integrated across DDC mode SINAD Calibration = BG 63.4 dBFS output bandwidth Interleaving spurs included FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 55.8 10.3 Effective number of bits, FIN = 600 MHz, –1 dBFS, decimate-by-8 integrated across DDC output mode ENOB Calibration = BG 10.2 Bits bandwidth Interleaving spurs included FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 9.0 76.2 Spurious-free dynamic range FIN = 600 MHz, –1 dBFS, decimate-by-8 SFDR dBFS Interleaving Spurs Included mode Calibration = BG 76.7 –73 Interleaving offset spur at ½ FIN = 600 MHz, –1 dBFS, decimate-by-8 ƒS/2 dBFS sampling rate (3) mode Calibration = BG –72 (3) Magnitude of reported tones in output spectrum of ADC core. This tone will only be present in the DDC output for specific Decimation and NCO settings. Careful frequency planning can be used to intentionally place unwanted tones outside the DDC output spectrum. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: ADC12J1600 ADC12J2700 |
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