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ADC12J1600 Datasheet(PDF) 89 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 89 Page - Texas Instruments |
89 / 98 page ![]() 0.0040'' 0.0041'' 0.0067'' 0.0040'' L1 ± SIG L2 ± GND L5 ± PWR L10 ± SIG L7 ± GND L6 ± SIG 1/2 oz. Copper on L1, L3, L6, L8, L10 1 oz. Copper on L2, L4, L5, L7, L9 100 Differential Signaling on SIG Layers Low loss dielectric adjacent very high speed trace layers Finished thickness 0.0620" including plating and solder mask 0.0578'' 0.0060'' L4 ± GND 0.0067'' L3 ± SIG 0.0073'' L9 ± GND L8 ± SIG 0.0040'' 0.0060'' VA19 VA12 VNEG VA19 VNEG VA12 VA19 VIN+ VIN± VCMO VA19 DEVCLK+ VA12 RBIAS+ VA12 RBIAS± DEVCLK± VD12 DS2± DS2+ VD12 DS3± DS3+ DS6+/NCO_1 DS6±/NCO_1 VD12 DS5+/NCO_0 DS5±/NCO_0 DS4+ DS4± VD12 VD12 DS1± DS1+ 1 17 35 51 2 3 4 5 7 6 8 9 10 11 12 13 14 15 16 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Additional decoupling capacitors near device. Decoupling capacitors power pins near VIN and DEVCLK on this side of board. RBIAS resistor near to RBIAS+ and RBIAS- pins. Larger bulk decoupling capacitors on this side of board, near device. Optional differential VIN path selected if capacitors or resistors installed here. DEVCLK path A selected if capacitors installed here. ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Layout Example (continued) Figure 116. ADC12J1600 and ADC12J2700 Layout Example 2 — Bottom Side Figure 117. ADC12J1600 and ADC12J2700 Typical Stackup — 10 Layer Board Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 89 Product Folder Links: ADC12J1600 ADC12J2700 |
Similar Part No. - ADC12J1600_16 |
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Similar Description - ADC12J1600_16 |
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