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ADC12J1600 Datasheet(PDF) 88 Page - Texas Instruments

Part # ADC12J1600
Description  GSPS ADCs With Integrated DDC
Download  98 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12J1600 Datasheet(HTML) 88 Page - Texas Instruments

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VA19
VA12
VNEG
VA19
VNEG
VA12
VA19
VIN+
VIN±
VCMO
VA19
DEVCLK+
VA12
RBIAS+
VA12
RBIAS±
DEVCLK±
VD12
DS2±
DS2+
VD12
DS3±
DS3+
DS6+/NCO_1
DS6±/NCO_1
VD12
DS5+/NCO_0
DS5±/NCO_0
DS4+
DS4±
VD12
VD12
DS1±
DS1+
1
17
35
51
2
3
4
5
7
6
8
9
10
11
12
13
14
15
16
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Straight analog input path with
minimal adjacent circuitry.
Straight DEVCLK path with
minimal adjacent circuitry.
Balun transformer for SE to
differential conversion.
Power supply decoupling capacitors
very close to power pins.
Power supply
decoupling
capacitors near
VIN and DEVCLK
are located on
opposite side of
board to minimize
noise coupling.
AC coupling capacitors on serial
output pairs.
GND reference vias near where high
speed signals transition to inner layer.
DEVCLK path B
selected if capacitors
installed here.
Single ended VIN
path via balun
selected if capacitors
installed here.
Large bulk
decoupling
capacitor near
device.
ADC12J1600, ADC12J2700
SLAS969C – JANUARY 2014 – REVISED JULY 2015
www.ti.com
Layout Guidelines (continued)
Coupling onto or between the clock and input signal paths must be avoided using any isolation techniques
available including distance isolation, orientation planning to prevent field coupling of components like inductors
and transformers, and providing well coupled reference planes. Via stitching around the clock signal path and the
input analog signal path provides a quiet ground reference for the critical signal paths and reduces noise
coupling onto these paths. Sensitive signal traces must not cross other signal traces or power routing on
adjacent PCB layers, rather a ground plane must separate the traces. If necessary, the traces should cross at
90° angles to minimize crosstalk.
Isolation of the analog input is important because of the low-level drive required of the ADC12J1600 and
ADC12J2700 devices. Quality analog input signal and clock signal path layout is required for full dynamic
performance. Symmetry of the differential signal paths and discrete components in the path is mandatory and
symmetrical shunt-oriented components should have a common grounding via. The high frequency requirements
of the input and clock signal paths necessitate using differential routing with controlled impedances and
minimizing signal path stubs (including vias) when possible.
Layout of the high-speed serial-data lines is of particular importance. These traces must be routed as tightly
coupled 100-
Ω differential pairs, with minimal vias. When vias must be used, care must be taken to implement
control-impedance vias (that is, 50-
Ω) with adjacent ground vias for image current control.
10.2 Layout Example
The following examples show layout-example plots (top and bottom layers only). Figure 117 shows a typical
stackup for a 10 layer board.
Figure 115. ADC12J1600 and ADC12J2700 Layout Example 1 — Top Side
88
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Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: ADC12J1600 ADC12J2700


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