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ADC12J1600 Datasheet(PDF) 84 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 84 Page - Texas Instruments |
84 / 98 page ![]() ADC JESD204 Receiver 8 Lanes SPI Master Over-Range Logic Data Processing / Storage JESD204 Clock Generator SYSREF and FPGA CLKs SYNC~ VCMO LMH6518 Output Amp LMH6518 Aux Amp Trigger Logic LMH7220 DAC DAC101C085 JFET LNA 1 nF MUX 900 k 90 k 10 k 50 Hi-Z 50- Switch Gain Control DISPLAY Memory Interface Display Interface MEMORY MEMORY MEMORY + Frequency (MHz) 0 80 160 240 320 400 480 560 640 720 800 -125 -100 -75 -50 -25 0 D095 Frequency (MHz) -25 -12.5 0 12.5 25 -120 -100 -80 -60 -40 -20 0 D094 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com DDC Bypass Mode ƒS = 1600 MSPS ƒS = 1600 MSPS ƒ(NCO) = 2500 MHz FIN = 2497.97 MHz at –1 dBFS FIN = 2497.97 MHz at –1 dBFS Figure 110. Spectrum — DDC Bypass Mode Figure 111. Spectrum — Decimate-by-32 8.2.2 Oscilloscope The ADC12J1600 and ADC12J2700 devices are equally well-suited for high-speed time-domain applications such as oscilloscopes. The following typical application is for a generic high-speed oscilloscope. Adjustable gain is provided by the front-end resistor ladder and selection mux, and the gain adjustments of the LMH6518 device. Additional gain fine-tuning can be achieved using the full-scale range adjustment features of the ADC. Figure 112. Simplified Schematic for an Oscilloscope 84 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 |
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