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ADC12J1600 Datasheet(PDF) 81 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 81 Page - Texas Instruments |
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81 / 98 page  ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.7.14 NCO Phase (Preset x) Register (address = see Table 71) [reset = see Table 71] Figure 107. NCO Phase (Preset) Register (NCO_PHASE_x) 15 14 13 12 11 10 9 8 NCO_PHASE_x R/W-0x00h 7 6 5 4 3 2 1 0 NCO_PHASE_x R/W-0x00h Table 85. NCO_PHASE_x Field Descriptions Bit Field Type Reset Description 15-0 NCO_PHASE_x R/W 0x0000h This value is MSB-justified into a 32 −bit field and then added to the phase accumulator. The phase (in radians) is NCO_PHASE_x × 2 –16 × 2π (16) This register can be interpreted as signed or unsigned. 7.6.1.7.15 DDC Delay (Preset x) Register (address = see Table 71) [reset = see Table 71] Figure 108. DDC Delay (Preset) Register (DDC_DLY_x) 7 6 5 4 3 2 1 0 DDC_DLY_x R/W-0xFFh Table 86. DDC_DLY_x Field Descriptions Bit Field Type Reset Description 7-0 DDC_DLY_x R/W 0xFFh DDC delay for configuration preset 0 This register provides fine adjustments to the DDC group delay. The step size is one half of an ADC sample period (t(DEVCLK) / 2). This is equivalent to Equation 17. tO / (2 × D) where • tO is the DDC output sample period • D is the decimation factor (17) The legal range for this register is 0 to 2D-1. Illegal values result in undefined behavior. Example: When D = 8, the legal register range is 0 to 15. The step size is tO / 16 and the maximum delay is 15 × tO / 16. Programming this register to 0xFF (the default value) powers down and bypasses the fractional delay filter which reduces the DDC latency by 34 ADC sample periods (as compared to the 0 setting). Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 81 Product Folder Links: ADC12J1600 ADC12J2700 |
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