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ADC12J1600 Datasheet(PDF) 76 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 76 Page - Texas Instruments |
76 / 98 page ![]() ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1.7.5 JESD204B Control 3 Register (address = 0x204) [reset = 0x00] Figure 98. JESD204B Control 3 Register (JESD_CTRL3) 7 6 5 4 3 2 1 0 RESERVED FCHAR R/W-0000 00 R/W-00 Table 76. JESD_CTRL3 Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0000 00 1-0 FCHAR(1) R/W 00 Specify which comma character is used to denote end-of-frame. This character is transmitted opportunistically according to JESD204B Section 5.3.3.4. When using a JESD204B receiver, always use FCHAR=0. When using a general purpose 8-b or 10-b receiver, the K28.7 character can cause issues. When K28.7 is combined with certain data characters, a false, misaligned comma character can result, and some receivers realign to the false comma. To avoid this, program FCHAR to 1 or 2. 0 : Use K28.7 (default) (JESD204B compliant) 1 : Use K28.1 (not JESD204B compliant) 2 : Use K28.5 (not JESD204B compliant) 3 : Reserved (1) The JESD_CTRL3 register must only be changed when JESD_EN is 0. 7.6.1.7.6 JESD204B and System Status Register (address = 0x205) [reset = Undefined] See the JESD204B Synchronization Features section for more details. Figure 99. JESD204B and System Status Register (JESD_STATUS) 7 6 5 4 3 2 1 0 RESERVED LINK_UP SYNC_STATUS REALIGNED ALIGNED PLL_LOCKED RESERVED R/W-0 R/W-0 R/W-X R/W-X R/W-0 R/W-0 R/W-00 Table 77. JESD_STATUS Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0 Always returns 0 6 LINK_UP R/W 0 When set, indicates that the JESD204B link is in the DATA_ENC state. 5 SYNC_STATUS R/W X Returns the state of the JESD204B SYNC~ signal (SYNC_SE_N or SYNC_DIFF_N). 0 : SYNC~ asserted 1 : SYNC~ deasserted 4 REALIGNED R/W X When high, indicates that the div8 clock, frame clock, or multiframe clock phase was realigned by SYSREF. Writing a 1 to this bit clears it. 3 ALIGNED R/W 0 When high, indicates that the multiframe clock phase has been established by SYSREF. The first SYSREF event after enabling the JESD204B encoder will set this bit. Writing a 1 to this bit clears it. 2 PLL_LOCKED R/W 0 When high, indicates that the PLL is locked. 1-0 RESERVED R/W 0 Always returns 0 76 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 |
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