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ADC12J1600 Datasheet(PDF) 75 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 75 Page - Texas Instruments |
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75 / 98 page  ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.7.3 JESD204B Control 2 Register (address = 0x202) [reset = 0x00] Figure 96. JESD204B Control 2 Register (JESD_CTRL2) 7 6 5 4 3 2 1 0 P54 SYNC_DIFFSEL RESERVED JESD204B_TEST R/W-0 R/W-0 R/W-00 R/W-0000 Table 74. JESD_CTRL2 Field Descriptions Bit Field Type Reset Description 7 P54 R/W 0 0 : Disable 5/4 PLL. Serial bit rate is 1x or 2x based on DDR parameter. 1 : Enable 5/4 PLL. Serial bit rate is 1.25x or 2.5x based on DDR parameter. 6 SYNC_DIFFSEL R/W 0 0 : Use SYNC_SE_N input for SYNC_N function 1 : Use SYNC_DIFF_N input for SYNC_N function 5-4 RESERVED R/W 00 Set to 00b 3-0 JESD204B_TEST(1) R/W 0000 See 0 : Test mode disabled. Normal operation (default) 1 : PRBS7 test mode 2 : PRBS15 test mode 3 : PRBS23 test mode 4 : Ramp test mode 5 : Short and long transport layer test mode 6 : D21.5 test mode 7 : K28.5 test mode 8 : Repeated ILA test mode 9 : Modified RPAT test mode 10: Serial outputs held low 11: Serial outputs held high 12 through 15 : RESERVED (1) The JESD_CTRL2 register must only be changed when JESD_EN is 0. 7.6.1.7.4 JESD204B Device ID (DID) Register (address = 0x203) [reset = 0x00] Figure 97. JESD204B Device ID (DID) Register (JESD_DID) 7 6 5 4 3 2 1 0 JESD_DID R/W-0000 0000 Table 75. JESD_DID Field Descriptions Bit Field Type Reset Description 7-0 JESD_DID(1) R/W 0000 0000 Specifies the DID value that is transmitted during the second multiframe of the JESD204B ILA. (1) The DID setting must only be changed when JESD_EN is 0. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 75 Product Folder Links: ADC12J1600 ADC12J2700 |
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