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ADC12J1600 Datasheet(PDF) 74 Page - Texas Instruments

Part # ADC12J1600
Description  GSPS ADCs With Integrated DDC
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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ADC12J1600 Datasheet(HTML) 74 Page - Texas Instruments

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ADC12J1600, ADC12J2700
SLAS969C – JANUARY 2014 – REVISED JULY 2015
www.ti.com
7.6.1.7.1
Digital Down-Converter (DDC) Control Register (address = 0x200) [reset = 0x10]
Figure 94. Digital Down-Converter (DDC) Control Register (DDC_CTRL1)
7
6
5
4
3
2
1
0
RESERVED
SFORMAT
DDC GAIN
DMODE
BOOST
R/W-00
R/W-0
R/W-1
R/W-0000
Table 72. DDC_CTRL1 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
00
5
SFORMAT
R/W
0
Output sample format for bypass mode:
0 : Offset binary (default)
1 : Signed 2s complement(1)
4
DDC GAIN BOOST
R/W
1
0 : Final filter has 0-dB gain (recommended when NCO is set
near DC).
1 : Final filter has 6.02-dB gain (default)
3-0
DMODE(2)
R/W
0000
0 : Bypass mode (12-bit output, decimate-by-1, DDC off)
(default)
1 : Reserved
2 : decimate-by-4
3 : decimate-by-8
4 : decimate-by-10
5 : decimate-by-16
6 : decimate-by-20
7 : decimate-by-32
8..15 : RESERVED
(1)
Decimated modes always output in signed 2s complement.
(2)
The DMODE setting must only be changed when JESD_EN is 0.
7.6.1.7.2
JESD204B Control 1 Register (address = 0x201) [reset = 0x0F]
Figure 95. JESD204B Control 1 Register (JESD_CTRL1)
7
6
5
4
3
2
1
0
SCR
K_Minus_1
DDR
JESD_EN
R/W-0
R/W-000 11
R/W-1
R/W-1
Table 73. JESD_CTRL1 Field Descriptions
Bit
Field
Type
Reset
Description
7
SCR
R/W
0
0 : Scrambler disabled (default)
1 : Scrambler enabled
6-2
K_Minus_1
R/W
000 11
K is the number of frames per multiframe, and K – 1 is
programmed here.
Default: K = 4, K_Minus_1 = 3.
Depending on the decimation (D) and serial rate (DDR), there
are constraints on the legal values of K.
1
DDR
R/W
1
0 : SDR serial rate (ƒ(BIT) = ƒS)
1 : DDR serial rate (ƒ(BIT) = 2ƒS) (default)
0
JESD_EN(1)
R/W
1
0 : Block disabled
1 : Normal operation (default)
(1)
Before altering any parameters in the JESD_CTRL1 register, you must set JESD_EN to 0. When JESD_EN is 0, the block is held in
reset and the serializers are powered down. The clocks are gated off to save power.
74
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Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: ADC12J1600 ADC12J2700


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