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ADC12J1600 Datasheet(PDF) 68 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 68 Page - Texas Instruments |
68 / 98 page ![]() ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1.5 Serializer (0x040 to 0x04F) Table 61. Serializer Registers Address Reset Acronym Register Name Section 0x040 0x04 SER_CFG Serializer Configuration Register Go 0x041-0x04F Undefined RESERVED RESERVED 7.6.1.5.1 Serializer Configuration Register (address = 0x040) [reset = 0x04] Figure 86. Serializer configuration Register (SER_CFG) 7 6 5 4 3 2 1 0 RESERVED SERIALIZER PRE-EMPHASIS R/W-0000 R/W-0100 Table 62. SER_CFG Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0000 3-0 SERIALIZER PRE-EMPHASIS R/W 0100 Control bits for the pre-emphasis strength of the serializer output driver. Pre-emphasis is required to compensate the low pass behavior of the PCB trace. Default: 4d 68 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 |
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