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ADC12J1600 Datasheet(PDF) 66 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 66 Page - Texas Instruments |
66 / 98 page ![]() ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1.4.2 Clock Generator Status Register (address = 0x031) [reset = 0x07] Figure 82. Clock Generator Status Register (CLKGEN_1) 7 6 5 4 3 2 1 0 SysRefDet Dirty Capture RESERVED R-0 R-0 R-00 0111 Table 57. CLKGEN_1 Field Descriptions Bit Field Type Reset Description 7 SysRefDet R 0 When high, indicates that a SYSREF rising edge was detected. To clear this bit, write SysRefDetClr to 1 and then back to 0. 6 Dirty Capture R 0 When high, indicates that a SYSREF rising edge occurred very close to the device clock edge, and setup or hold is not ensured (dirty capture). To clear this bit, write CDC to1 and then back to 0. NOTE: When sweeping the timing on SYSREF, it may jump across the clock edge without triggering this bit. The REALIGNED status bit must be used to detect this (see the JESD_STATUS register description in Digital Down Converter and JESD204B (0x200-0x27F)) 5-0 RESERVED R 00 0111 Reserved register. Always returns 000111b 7.6.1.4.3 Clock Generator Control 2 Register (address = 0x032) [reset = 0x80] Figure 83. Clock Generator Control 2 Register (CLKGEN_2) 7 6 5 4 3 2 1 0 RESERVED RDEL R/W-1000 R/W-0000 Table 58. CLKGEN_2 Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 1000 Default: 1000b 3-0 RDEL R/W 0000 Adjusts the delay of the SYSREF input signal with respect to DEVCLK. Each step delays SYSREF by 20 ps (nominal) Default: 0 Range: 0 to 15 decimal 66 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 |
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