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ADC12J1600 Datasheet(PDF) 65 Page - Texas Instruments

Part # ADC12J1600
Description  GSPS ADCs With Integrated DDC
Download  98 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12J1600 Datasheet(HTML) 65 Page - Texas Instruments

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ADC12J1600, ADC12J2700
www.ti.com
SLAS969C – JANUARY 2014 – REVISED JULY 2015
7.6.1.4 Clock (0x030 to 0x03F)
Table 55. Clock Registers
Address
Reset
Acronym
Register Name
Section
0x030
0xC0
CLKGEN_0
Clock Generator Control 0 Register
Go
0x031
0x07
CLKGEN_1
Clock Generator Status Register
Go
0x032
0x80
CLKGEN_2
Clock Generator Control 2 Register
Go
0x033
0xC3
ANA_MISC
Analog Miscellaneous Register
Go
0x034
0x2F
IN_CL_EN
Clamp Enable Register
Go
0x035
0xDF
RESERVED
RESERVED
0x036
0x00
RESERVED
RESERVED
0x037
0x45
RESERVED
RESERVED
0x038-0x03F
Undefined
RESERVED
RESERVED
7.6.1.4.1
Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0]
Figure 81. Clock Generator Control 0 Register (CLKGEN_0)
7
6
5
4
3
2
1
0
SysRef_Rcvr_E
SysRef_Pr_En
SysRefDetClr
Clear Dirty
RESERVED
DC_LVPECL_C DC_LVPECL_S DC_LVPECL_T
n
Capture
LK_en
YSREF_en
S_en
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 56. CLKGEN_0 Field Descriptions
Bit
Field
Type
Reset
Description
7
SysRef_Rcvr_En
R/W
1
Default: 1
0 : SYSREF receiver is disabled.
1 : SYSREF receiver is enabled (default)
6
SysRef_Pr_En
R/W
1
To power down the SYSREF receiver, clear this bit first, then
clear SysRef_Rcvr_En. To power up the SYSREF receiver, set
SysRef_Rcvr_En first, then set this bit.
Default: 1
0 : SYSREF Processor is disabled.
1 : SYSREF Processor is enabled (default)
5
SysRefDetClr
R/W
0
Default: 0
Write a 1 and then a 0 to clear the SysRefDet status bit.
4
Clear Dirty Capture
R/W
0
Default: 0
Write a 1 and then a 0 to clear the DC status bit.
3
RESERVED
R/W
0
Default: 0
2
DC_LVPECL_CLK_en
R/W
0
Default: 0
Set this bit if DEVCLK is a DC-coupled LVPECL signal through
a 50-
Ω resistor.
1
DC_LVPECL_SYSREF_en
R/W
0
Default: 0
Set this bit if SYSREF is a DC-coupled LVPECL signal through
a 50-
Ω resistor.
0
DC_LVPECL_TS_en
R/W
0
Default: 0
Set this bit if TimeStamp is a DC-coupled LVPECL signal
through a 50-
Ω resistor.
Copyright © 2014–2015, Texas Instruments Incorporated
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Product Folder Links: ADC12J1600 ADC12J2700


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