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ADC12J1600 Datasheet(PDF) 63 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 98 page  ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.3 General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F) Table 49. General Analog, Bias, Band Gap, and Track and Hold Registers Address Reset Acronym Register Name Section 0x020 0x9D RESERVED RESERVED 0x021 0x00 POR Power-On Reset Register Go 0x022 0x40 IO_GAIN_0 I/O Gain 0 Register Go 0x023 0x00 IO_GAIN_1 I/O Gain 1 Register Go 0x024 0x00 RESERVED RESERVED 0x025 0x40 IO_OFFSET_0 I/O Offset 0 Register Go 0x026 0x00 IO_OFFSET_1 I/O Offset 1 Register Go 0x027 0x06 RESERVED RESERVED 0x028 0xBA RESERVED RESERVED 0x029 0xD4 RESERVED RESERVED 0x02A 0xAA RESERVED RESERVED 0x02B-0x02F Undefined RESERVED RESERVED 7.6.1.3.1 Power-On Reset Register (address = 0x021) [reset = 0x00] Figure 76. Power-On Reset Register (POR) 7 6 5 4 3 2 1 0 RESERVED SPI_RES R/W-0000 000 R/W-0 Table 50. POR Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0000 000 0 SPI_RES R/W 0 Reset all digital. Emulates a power on reset (not self-clearing). Write a 0 and then write a 1 to emulate a reset. Transition from 0—>1 initiates reset. Default: 0 7.6.1.3.2 I/O Gain 0 Register (address = 0x022) [reset = 0x40] Figure 77. I/O Gain 0 Register (IO_GAIN_0) 7 6 5 4 3 2 1 0 RESERVED GAIN_FS[14] GAIN_FS[13] GAIN_FS[12] GAIN_FS[11] GAIN_FS[10] GAIN_FS[9] GAIN_FS[8] R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 51. IO_GAIN_0 Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0 6-0 GAIN_FS[14:8] R/W 100 0000 MSB Bits for GAIN_FS[14:0]. (See the IO_GAIN_1 description in General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)) Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 63 Product Folder Links: ADC12J1600 ADC12J2700 |
Similar Part No. - ADC12J1600_16 |
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Similar Description - ADC12J1600_16 |
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