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ADC12J1600 Datasheet(PDF) 61 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 61 Page - Texas Instruments |
61 / 98 page ![]() ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.1.3 Device Configuration Register (address = 0x002) [reset = 0x00] Figure 71. Device Configuration Register (DEVCFG) 7 6 5 4 3 2 1 0 RESERVED MODE R/W-000000 R/W-00 Table 43. DEVCFG Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0000 00 1-0 MODE R/W 00 SPI 3.0 specification has 1 as low power functional mode and 2 as low power fast resume. This chip does not support these modes. 0: Normal Operation – full power and full performance (default) 1: Normal Operation – full power and full performance (default) 2: Power Down – Everything powered down 3: Power Down – Everything powered down 7.6.1.1.4 Chip Type Register (address = 0x003) [reset = 0x03] Figure 72. Chip Type Register (CHIP_TYPE) 7 6 5 4 3 2 1 0 RESERVED CHIP_TYPE R-0000 R-0011 Table 44. CHIP_TYPE Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0000 3-0 CHIP_TYPE R 0011 Always returns 0x3, indicating that the part is a high speed ADC. 7.6.1.1.5 Chip Version Register (address = 0x006) [reset = 0x03] Figure 73. Chip Version Register (CHIP_VERSION) 7 6 5 4 3 2 1 0 CHIP_VERSION R-0000 0011 Table 45. CHIP_VERSION Field Descriptions Bit Field Type Reset Description 7-0 CHIP_VERSION R 0000 0011 Chip version, returns 0x03 Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 61 Product Folder Links: ADC12J1600 ADC12J2700 |
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Similar Description - ADC12J1600_16 |
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