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ADC12J1600 Datasheet(PDF) 52 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 52 Page - Texas Instruments |
52 / 98 page ![]() DDC ADC JESD204B Transport Layer Scrambler JESD204B Link Layer JESD204B TX ADC Test Pattern Enable Long or Short Transport Octet Ramp Test Mode Enable Repeated ILA Modified RPAT Test Mode Enable PRBSn D21.5 K28.5 Serial Outputs High/Low Test Mode Enable Active Lanes and Serial Rates Set by D, DDR, and P54 Parameters 8b10b Encoder ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Table 33. ADC Test Pattern(1) LANE (CONVERTER SAMPLE NUMBER (SID) ID) 0 1 2 3 4 5 6 7 8 9 0 0x000 0xFFF 0x000 0xFFF 0x000 0xFFF 0x000 0xFFF 0x000 0xFFF 1 0x008 0xFF7 0x008 0xFF7 0x008 0xFF7 0x008 0xFF7 0x008 0xFF7 2 0x010 0xFEF 0x010 0xFEF 0x010 0xFEF 0x010 0xFEF 0x010 0xFEF 3 0x020 0xFDF 0x020 0xFDF 0x020 0xFDF 0x020 0xFDF 0x020 0xFDF 4 0x040 0xFBF 0x040 0xFBF 0x040 0xFBF 0x040 0xFBF 0x040 0xFBF 5 0x100 0xEFF 0x100 0xEFF 0x100 0xEFF 0x100 0xEFF 0x100 0xEFF 6 0x200 0xDFF 0x200 0xDFF 0x200 0xDFF 0x200 0xDFF 0x200 0xDFF 7 0x400 0xBFF 0x400 0xBFF 0x400 0xBFF 0x400 0xBFF 0x400 0xBFF (1) When background-calibration mode is enabled, the pattern values are dynamic because the internal converter banks are output on different lanes during the calibration bank-switching process. Each converter bank has dedicated pattern values as listed in Table 34. Table 34. ADC Bank Pattern Values BANK LOCATION LOW VALUE HIGH VALUE Lane n 0x000 0xFFF 0 Lane n+4 0x040 0xFBF Lane n 0x004 0xFFE 1 Lane n+4 0x080 0xF7F Lane n 0x008 0xFF7 2 Lane n+4 0x100 0xEFF Lane n 0x010 0xFEF 3 Lane n+4 0x200 0xDFF Lane n 0x020 0xFDF 4 Lane n+4 0x400 0xBFF 7.4.5.2 Serializer Test-Mode Details Test modes are enabled by setting the appropriate configuration of the JESD204B_TEST setting (Register 0x202, Bits 3:0). Each test mode is described in detail in the following sections. Regardless of the test mode, the serializer outputs are powered up based on the configuration decimation and DDR settings. The test modes should only be enabled while the JESD204B link is disabled. Figure 66. Test-Mode Insertion Points 52 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 |
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