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ADC12J1600 Datasheet(PDF) 51 Page - Texas Instruments

Part # ADC12J1600
Description  GSPS ADCs With Integrated DDC
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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ADC12J1600 Datasheet(HTML) 51 Page - Texas Instruments

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ADC12J1600, ADC12J2700
www.ti.com
SLAS969C – JANUARY 2014 – REVISED JULY 2015
Device Functional Modes (continued)
Table 32. Calibration Cycle Timing for Different Calibration Modes and Options
INITIAL ONE-TIME
BACKGROUND
CALIBRATION
CALIBRATION CYCLE(1)
CAL_CONT, CAL_BCK
T_AUTO
LOW_SIG_EN
CAL_SFT 0
→ 1
(ALL CORES)
(tDEVCLK)
(tDEVCLK)
0
0
0
102 E+6
N/A
0
0
1
64 E+6
N/A
0
1
0
227 E+6
N/A
0
1
1
189 E+6
N/A
1
0
0
127.5 E+6
816 E+6
1
0
1
80 E+6
512 E+6
1
1
0
283.75 E+6
816 E+6
1
1
1
236.25 E+6
512 E+6
(1)
N/A = not applicable
7.4.5 Test-Pattern Modes
A number of device test modes are available. These modes insert known patterns of information into the device
data path for assistance with system debug, development, or characterization.
7.4.5.1 ADC Test-Pattern Mode
The 12-bit ADC core has a built-in test-pattern generator. This mode is helpful for verifying the full data link from
the ADC to the data receiver when in DDC bypass mode. When the test-pattern mode is enabled, the ADC
output data is replaced by a pattern that repeats every two frames. The data sequence is is shown in Table 33
(shown for default settings with foreground calibration mode).
Copyright © 2014–2015, Texas Instruments Incorporated
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Product Folder Links: ADC12J1600 ADC12J2700


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