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ADC12J1600 Datasheet(PDF) 49 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 49 Page - Texas Instruments |
49 / 98 page ![]() ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 As long as the SYSREF signal has a fixed timing relationship to DEVCLK, the internal delay can be used to maximize the setup and hold times between the internally delayed SYSREF and the internal DEVCLK signal. These timing relationships are listed in the Timing Requirements table. To find the proper delay setting, the RDEL value is adjusted from minimum to maximum while applying SYSREF and monitoring the SysRefDet and Dirty Capture detect bits. The SysRefDet bit is set whenever a rising edge of SYSREF is detected. The Dirty Capture bit is set whenever the setup or hold time between DEVCLK and the delayed SYSREF is insufficient. The SysRefDetClr bit is used to clear the SysRefDet bit. The Clear Dirty Capture bit is used to clear that bit. This procedure should be followed to determine the range of delay settings where a clean SYSREF capture is achieved. The delay value at the center of the clean capture range must be loaded as the final RDEL setting. Table 31 lists a summary of the control bits that are used and the monitor bits that are read. Table 31. SYSREF Capture Control and Status BIT NAME REGISTER ADDRESS REGISTER BIT FUNCTION RDEL 0x032 3:0 Adjust relative delay between DEVCLK and SYSREF SysRefDet 0x031 7 Detect if a SYSREF rising edge has been captured (not self clearing) Dirty Capture 0x031 6 Detect if SYSREF rising edge capture failed setup/hold (not self clearing) SysRefDetClr 0x030 5 Clear SYSREF detection bit Clear Dirty Capture 0x030 4 Clear Dirty Capture detection bit Enable SYSREF receiver. See the CLKGEN_0 descriptions in the Clock Generator Control 0 Register section SysRef_Rcvr_En 0x030 7 for more information. Enable SYSREF processing. See the CLKGEN_0 descriptions in the Clock Generator Control 0 Register SysRef_Pr_En 0x030 6 section for more information. One final aspect of multi-device synchronization relates to phase alignment of the NCO phase accumulators when DDC modes are enabled. The NCO phase accumulators are reset during the ILA phase of link startup which means that for multiple ADCs to have NCO phase alignment, all links must be enabled in the same LMFC period. Enabling all links in the same LMFC period requires synchronizing the SYNC~ de-assertion across all data receivers in the system, so that all of the SYNC~ signals are released during the same LMFC period. Using large K values and resulting longer LMFC periods will ease this task, at the expense of potentially higher latency in the receiving device. 7.4 Device Functional Modes 7.4.1 DDC Bypass Mode In DDC bypass mode (decimation = 1) the raw 12 bit data from the ADC is output at the full sampling rate. 7.4.2 DDC Modes In the DDC modes (decimation > 1) complex (I,Q) data is output at a lower sample rate as determined by the decimation factor (4, 8, 10, 16, 20, and 32). 7.4.3 Calibration Calibration adjusts the ADC core to optimize the following device parameters: • ADC core linearity • ADC core-to-core offset matching • ADC core-to-core full-scale range matching • ADC core 4-way interleave timing All calibration processes occur internally. Calibration does not require any external signals to be present and works properly as long as the device is maintained within the values listed in the Recommended Operating Conditions table. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Links: ADC12J1600 ADC12J2700 |
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