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ADC12J1600 Datasheet(PDF) 48 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 98 page  ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.3.7.2.8 JESD204B Synchronization Features The JESD204B standard defines methods for synchronization and deterministic latency in a multi-converter system. These devices are a JESD204B Subclass 1 device and conforms to the various aspects of link operation as described in section 5.3.3 of the JESD204B standard. The specific signals used to achieve link operation are described briefly in the following sections. 7.3.7.2.9 SYSREF The SYSREF is a periodic signal which is sampled by the device clock, and is used to align the boundary of the local multi-frame clock inside the data converter. SYSREF is required to be a sub-harmonic of the LMFC internal timing. To meet this requirement, the timing of SYSREF is dependent on the device clock frequency and the LMFC frequency as determined by the selected DDC decimation and frames per multi-frame settings. This clock is typically in the range of 10 MHz to 300 MHz. See the Multiple ADC Synchronization section for more details on SYSREF timing requirements. 7.3.7.2.10 SYNC~ SYNC~ is asserted by the receiver to initiate a synchronization event. Single ended and differential SYNC~ inputs are provided. The SYNC_DIFFSEL bit (register 0x202, bit 6) is used to select which input is used. Using the single ended SYNC~ input is recommended, as this frees the differential SYNC~/TMST input pair for use in the Time Stamp function. To assert SYNC~, a logic low is applied. To deassert SYNC~ a logic high is applied. 7.3.7.2.11 Time Stamp When configured through the TIME_STAMP_EN register setting (register 0x050, bit 5), the SYNC~ differential input (pins 22 and 23) can be used as a time-stamp input. The time-stamp feature enables the user to capture the timing of an external trigger event relative to the sampled signal. When enabled, the LSB of the 12-bit ADC digital output captures the trigger information. In effect, the 12-bit converter becomes an 11-bit converter and the LSB acts as a 1-bit converter with the same latency as the 11-bit converter. The trigger must be applied to the differential SYNC~/TMST inputs. The trigger can be asynchronous to the ADC sampling clock and is sampled at approximately the same time as the analog input. 7.3.7.2.12 Code-Group Synchronization Code-group synchronization is achieved using the following process: • The receiver issues a synchronization request through the SYNC~ input • The transmitter issues a stream of K28.5 symbols • The receiver synchronizes and waits for correct reception of at least 4 consecutive K symbols • The receiver deactivates the synchronization request • Upon detecting that the receiver has deactivated the SYNC~ pin, the transmitter continues emitting K symbols until the next LMFC boundary (or optionally a later LMFC boundary) • On the first frame following the selected LMFC boundary the transmitters emit an initial lane-alignment sequence The initial-lane alignment sequence transmitted by the ADC device is defined in additional detail in JESD204B section 5.3.3.5. 7.3.7.2.13 Multiple ADC Synchronization The second function for the SYSREF input is to facilitate the precise synchronization of multiple ADCs in a system. One key challenge is to ensure that this synchronization works is to ensure that the SYSREF inputs are repeatedly captured by the input CLK. Two key elements must occur for the SYSREF inputs to be captured. First, the SYSREF input must be created so that it is synchronous to the input DEVCLK, be an integer sub- harmonic of the multi-frame (K × t(FRAME)) and a repeatable and fixed-phase offset. When this constraint is achieved, repeatedly capturing SYSREF is easier. To further ease this task, the SYSREF signal is routed through a user-adjustable delay which eases the timing requirements with respect to the input DEVCLK signal. The SYSREF delay RDEL is adjusted through bits 3 through 0 in register 0x032. 48 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 |
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