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ADC12J1600 Datasheet(PDF) 47 Page - Texas Instruments

Part # ADC12J1600
Description  GSPS ADCs With Integrated DDC
Download  98 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12J1600 Datasheet(HTML) 47 Page - Texas Instruments

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ADC12J1600, ADC12J2700
www.ti.com
SLAS969C – JANUARY 2014 – REVISED JULY 2015
Table 25. Decimate-by-16, DDR = 1, P54 = 1, LMF = 1,2,4
TIME
→
CHAR NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
Lane 0
I0
Q0
I1
Q1
I2
Q2
Frame n
Frame n + 1
Frame n + 2
Table 26. Decimate-by-20, DDR = 0, P54 = 0, LMF = 2,2,2
TIME
→
CHAR NUMBER
0
1
2
3
4
5
6
7
Lane 0
I0
I1
I2
I3
Lane 1
Q0
Q1
Q2
Q3
Frame
Frame
Frame
Frame
n
n + 1
n + 2
n + 3
Table 27. Decimate-by-20, DDR = 1, P54 = 0, LMF = 1,2,2
TIME
→
CHAR NUMBER
0
1
2
3
4
5
6
7
Lane 0
I0
Q0
I1
Q1
Frame n
Frame n + 1
Table 28. Decimate-by-32, DDR = 0, P54 = 0, LMF = 2,2,16
TIME
→
CHAR
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NUMBER
Lane 0
I0
I1
I2
I3
I4
Q0
Q1
Q2
Lane 1
Q3
Q4
T
T
T
T
T
T
Frame n
Table 29. Decimate-by-32, DDR = 0, P54 = 1, LMF = 1,2,4
TIME
→
CHAR NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
Lane 0
I0
Q0
I1
Q1
I2
Q2
Frame n
Frame n + 1
Frame n + 2
Table 30. Decimate-by-32, DDR = 1, P54 = 0, LMF = 1,2,32
TIME
→
CHAR
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NUMBE
R
Lane 0
I0
I1
I2
I3
I4
Q0
Q1
Q2
Q3
Q4
T
T
T
T
T
T
Frame n
The formatted data is 8b10b encoded and output on the serial lanes. The 8b10b encoding provides a number of
specific benefits, including:
•
Standard encoding format. Therefore the IP is readily available in off-the-shelf FPGAs and ASIC building
blocks.
•
Inherent DC balance allows AC coupling of lanes with small on-chip capacitors
•
Inherent error checking
Copyright © 2014–2015, Texas Instruments Incorporated
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Product Folder Links: ADC12J1600 ADC12J2700


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