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ADC12J1600 Datasheet(PDF) 44 Page - Texas Instruments

Part # ADC12J1600
Description  GSPS ADCs With Integrated DDC
Download  98 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12J1600 Datasheet(HTML) 44 Page - Texas Instruments

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ADC12J1600, ADC12J2700
SLAS969C – JANUARY 2014 – REVISED JULY 2015
www.ti.com
Table 11. Serial Link Parameters(1) (continued)
USER SPECIFIED PARAMETERS
DERIVED PARAMETERS
OTHER INFORMATION
DECIMATION
LEGAL K
BIT RATE / ADC
DDR
P54
N
CS
N’
L
F
M
S
KS
FACTOR (D)
RANGE
CLOCK(2)
16
1
0
15
1
16
2
16
2
5
1
2-32
2x
16
1
1
15
1
16
1
4
2
1
1
5-32
2.5x
20
0
0
15
1
16
2
2
2
1
4
12-32
1x
20
1
0
15
1
16
1
4
2
1
4
8-32
2x
32
0
0
15
1
16
2
16
2
5
1
2-32
1x
32
0
1
15
1
16
1
4
2
1
1
5-32
1.25x
32
1
0
15
1
16
1
32
2
5
1
1-32
2x
Output data is formatted in a specific optimized fashion for each decimation and DDR setting combination. For
bypass mode (decimation = 1) the 12-bit offset binary values are mapped to the 8-bit characters. For the DDC
mode the 16-bit values (15-bit complex data plus 1 bit OR_Tn) are mapped to the 8-bit characters. The following
tables list the specific mapping formats. In all mappings the T or tail bits are 0 (zero).
Table 12. Bypass Mode, No Decimation, DDR = 1, P54 = 0, LMF = 8,8,8
TIME
CHAR
0
1
2
3
4
5
6
7
NUMBER
Lane 0
C0S0
C0S1
C0S2
C0S3
C0S4
T
Lane 1
C1S0
C1S1
C1S2
C1S3
C1S4
T
Lane 2
C2S0
C2S1
C2S2
C2S3
C2S4
T
Lane 3
C3S0
C3S1
C3S2
C3S3
C3S4
T
Lane 4
C4S0
C4S1
C4S2
C4S3
C4S4
T
Lane 5
C5S0
C5S1
C5S2
C5S3
C5S4
T
Lane 6
C6S0
C6S1
C6S2
C6S3
C6S4
T
Lane 7
C7S0
C7S1
C7S2
C7S3
C7S4
T
Frame n
Table 13. Bypass Mode, No Decimation, DDR = 1, P54 = 0, Composite View of Interleaved Converters
TIME
CHAR
0
1
2
3
4
5
6
7
NUMBER
Lane 0
S0
S8
S16
S24
S32
T
Lane 1
S1
S9
S17
S25
S33
T
Lane 2
S2
S10
S18
S26
S34
T
Lane 3
S3
S11
S19
S27
S35
T
Lane 4
S4
S12
S20
S28
S36
T
Lane 5
S5
S13
S21
S29
S37
T
Lane 6
S6
S14
S22
S30
S38
T
Lane 7
S7
S15
S23
S31
S39
T
Frame n
44
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